Series-Connected MOSFET Units for High Voltage Reliability
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Solution Overview
Problem
Conventional power semiconductor devices face challenges in improving operating voltage and reliability without excessively extending the gate length of MOSFETs, due to limitations in element size and process technology.
Innovation Solution
A power semiconductor device design incorporating two MOSFET units connected in series, with separate gate structures overlapping with doping regions of identical conductivity to the source and drain, allowing for improved voltage and reliability without extending the gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length of MOSFET is extended to prevent current leakage and improve operating voltage, then the reliability and operating voltage are improved, but the element size increases beyond design rule limitations and process technology constraints
Solution Approach 1:
The patent divides a single MOSFET into two series-connected MOSFET units (first and second transistor units) with separate gate structures. This segmentation allows each gate to be shorter than the equivalent single gate length, avoiding design rule violations while achieving the total voltage blocking capability of a longer gate through the series connection of the two units.
Solution Approach 2:
The patent introduces a vertical dimension by stacking two MOSFET units in series between source and drain, with a doping region connecting their gates. This three-dimensional arrangement achieves the electrical effect of a long gate (high voltage blocking) without requiring a proportionally long horizontal gate length, thus bypassing planar design rule constraints.
2Reliability
If the gate length of MOSFET is extended to prevent hot carrier injection and current leakage, then the operating voltage is improved, but the element size exceeds process technology limitations such as CMP technology
Solution Approach 1:
By segmenting the single MOSFET into two series-connected units, each with its own gate structure, the patent reduces the required length of each individual gate, making it compatible with existing CMP and other process technologies while maintaining the high voltage blocking capability through series connection.
Solution Approach 2:
The patent changes the electrical configuration from a single MOSFET to two series-connected MOSFET units, altering the voltage distribution parameters. Each unit handles a portion of the total voltage, allowing shorter gates that fit within process technology capabilities while achieving the same total voltage rating through the series arrangement.
3Reliability
If the gate length is extended to improve voltage operation, then the current leakage is reduced, but the design flexibility is reduced due to size constraints
Solution Approach 1:
By transitioning to a vertical stacking configuration with two MOSFET units connected in series, the patent achieves high voltage blocking (reduced current leakage) without proportionally increasing the lateral footprint. This preserves design flexibility for integration while achieving the desired electrical performance through three-dimensional device architecture.
Data Source
AI summary
A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.