Series Select Switches for 3D Memory Current Delivery
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Solution Overview
Problem
In three-dimensional memory arrays, select switches face challenges in providing sufficient current while occupying a small area, due to the increasing pitch and number of memory cells, which affects data reading and programming efficiency.
Innovation Solution
A select switch comprising two transistors connected in series, with separate gates that can be separately biased, is used between a horizontal global bit line and a vertical local bit line, allowing for increased current supply and better isolation without increasing die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single transistor is used as a select switch, then the device complexity is low, but the current delivery capability is insufficient
Solution Approach 1:
The select switch is segmented into two separate transistors (first select transistor and second select transistor) connected in series. Each transistor handles a portion of the switching function, collectively providing enhanced current delivery capability while maintaining manageable device complexity through modular segmentation.
2Area of stationary object
If the select switch size is reduced to occupy smaller die area, then the memory array density increases, but the current delivery capability decreases
Solution Approach 1:
The patent transitions from a planar single-transistor layout to a vertical stacked configuration with two transistors arranged in series along the vertical dimension. This dimensional change allows the select switch to achieve higher current delivery capability without increasing the horizontal die area, as the transistors are stacked vertically rather than placed side-by-side.
3Quantity of substance
If more memory cells are added to increase storage capacity, then the memory array size increases, but the pitch between cells increases requiring larger select switches
Solution Approach 1:
The select switch is segmented into two transistors working in series, which allows the overall switch structure to provide sufficient current delivery capability for larger memory arrays with increased cell pitch, while the segmented architecture can be optimized to fit within the available space between expanded cell structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current delivery to vertical bit lines and improves isolation between global and local bit lines, addressing the conflicting demands of smaller size and higher current requirements in three-dimensional memory structures.
Implementation Method 1
A select switch between a horizontal global bit line and a vertical local bit line, and comprising two transistors connected in series
Implementation Method 2
The two transistors have separate gates that can be separately biased to provide increased current to a vertical bit line compared with a single transistor, and to better isolate the vertical bit line from the global bit line
Data Source
AI summary
A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.