Series Turbo Decoder Parallelization for Lower Latency

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Solution Overview

Problem

Existing serial-concatenated turbo-decoders suffer from high latency due to idle periods caused by the sequential dependency between internal and external decoders, which limits throughput without proportionally increasing hardware resources.

Innovation Solution

The proposed solution involves parallel processing of intrinsic information items for both decoders, allowing the external decoder to initiate decoding without waiting for the internal decoder to complete, and implementing specialized algorithms and memory areas to manage extrinsic information efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential decoding is used where the external decoder waits for the internal decoder to complete, then decoding accuracy is maintained, but decoding latency increases and throughput decreases

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoding latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The external decoder performs preliminary decoding actions using available intrinsic information and previously stored extrinsic information before the internal decoder completes its processing. This allows the external decoder to start working in advance, reducing idle time and accelerating overall decoding throughput without compromising final decoding accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system maintains continuous useful action by enabling the external decoder to operate continuously using stored extrinsic information from previous iterations, rather than waiting idle for the internal decoder. This eliminates gaps in the decoding process and maximizes resource utilization, improving throughput while maintaining accuracy through iterative refinement.

Inventive Principle:
Principle #20Continuity of useful action

2Loss of time

If parallel processing is implemented to reduce latency, then decoding speed increases, but hardware resource requirements increase

Engineering Contradiction:
Improvedecoding latencyVSAvoidhardware resource requirements
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system merges the processing workflows of the internal and external decoders into a coordinated parallel operation. By sharing memory resources for extrinsic information storage and implementing synchronized processing steps, the system achieves parallel processing benefits without proportionally increasing hardware resources. The decoders work in parallel but share infrastructure, reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If the external decoder waits for extrinsic information from the internal decoder, then decoding accuracy is maintained, but idle periods increase reducing throughput

Engineering Contradiction:
Improvedecoder throughputVSAvoiddecoding accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The external decoder performs preliminary decoding using available intrinsic information and stores intermediate extrinsic information in memory before receiving refined information from the internal decoder. This preliminary action eliminates idle periods and maintains high throughput, while the subsequent refinement from the internal decoder ensures final decoding accuracy is maintained through iterative improvement.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12407365B2Decoding of series-concatenated turbo codes
Publication Date: 2025.09.02 ZODIAC DATA SYSTEMS
  • US12407365B2 patent drawing
  • US12407365B2 patent drawing
  • US12407365B2 patent drawing

AI summary

Series turbo-decoder, series turbo-decoding method and computer program product, the series turbo-decoder comprises an input configured to receive a word to be decoded comprising informative data or payload data, internal and external redundancy data, an internal decoder (DCI) and an external decoder (DCE). The internal decoder and the external decoder receive the word simultaneously. The internal decoder is configured to perform part of the decoding of the word based on the payload data and on the internal and external redundancy data. The external decoder is configured to perform another part of the decoding of the word based on the payload data and on the external redundancy data without awaiting the availability of information extrinsic to the internal decoder.