Vertically-serpentine gate field-effect transistors for chip area reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field-effect transistors in CMOS circuitry occupy a large area on chips, which is inefficient for high-frequency signal routing in mobile communication devices.
Innovation Solution
The structure includes a semiconductor substrate with trenches and a gate electrode configuration that extends along the trench sidewalls, allowing for a vertically-serpentine pattern without increasing the active device region's area, enabling longer gate electrodes without altering contact dimensions or spacings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode length is increased to improve high-frequency signal routing efficiency, then the signal routing efficiency is improved, but the chip area occupied by the field-effect transistor increases
Solution Approach 1:
The gate electrode is configured to extend vertically along the trench sidewalls instead of only horizontally, transforming the gate structure from a planar two-dimensional layout to a three-dimensional vertical structure. This allows the gate length to increase along the vertical dimension while maintaining a compact horizontal footprint, thereby improving high-frequency signal routing efficiency without increasing the chip area occupied by the transistor.
Solution Approach 2:
The gate electrode structure is nested within the trench formed in the semiconductor substrate. The trench provides a vertical cavity that accommodates the extended gate electrode along its sidewalls, allowing the gate to be embedded within the substrate structure rather than occupying additional surface area. This nesting approach enables longer gate electrodes to be integrated within the same chip footprint.
2Length of stationary object
If a vertically-serpentine gate configuration is implemented to increase gate electrode length, then the gate electrode length is increased, but the device structure complexity increases
Solution Approach 1:
The gate electrode is divided into multiple sections: a first section on the top surface, a second section on the bottom surface of the trench, and a third section along the sidewall. This segmentation allows the gate to follow the vertically-serpentine path through the trench, achieving extended gate length while maintaining a modular structure that can be fabricated using standard CMOS processes without excessive complexity.
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.