Serpentine Isolation Structure for High-Density DRAM Cell Fabrication
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing density and performance due to limitations in the design and fabrication of memory cells, particularly in volatile memory devices like DRAM cells.
Innovation Solution
A semiconductor device fabrication method involving a stack of polysilicon layers and isolation layers, with a serpentine-shaped trench and concave polysilicon structure, allows for the formation of a DRAM cell with optimized source, drain, and channel regions, along with a capacitor structure, to enhance density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell structures are used, then fabrication is simpler, but device density is limited
Solution Approach 1:
The patent transitions from planar memory cell layouts to a three-dimensional structure by forming a serpentine-shaped isolation layer that creates vertical stacking of source and drain regions. This dimensional change allows multiple memory cells to be stacked vertically, significantly increasing device density without proportionally increasing the footprint area.
Solution Approach 2:
The serpentine (curved/S-shaped) isolation layer is used to define the memory cell structure, replacing conventional straight-line isolation patterns. This curved geometry enables the source and drain regions to be positioned in a compact, space-efficient arrangement that increases cell density while maintaining manufacturability.
2Quantity of substance
If memory cell area is reduced to increase density, then device density improves, but manufacturing precision requirements increase
Solution Approach 1:
The memory cell is segmented into distinct functional regions defined by the serpentine isolation layer, including source regions, drain regions, and channel regions. This segmentation allows each region to be independently optimized and formed with controlled dimensions, reducing the impact of variability on overall device performance while maintaining high density.
Solution Approach 2:
Different regions of the memory cell structure are given different properties: the serpentine isolation layer provides mechanical definition and electrical isolation, while doped regions provide specific electrical characteristics. This local differentiation allows precise control of electrical properties in each zone without requiring uniform precision across the entire structure.
3Reliability
If conventional isolation shapes are used, then fabrication is easier, but device performance is limited
Solution Approach 1:
The serpentine (S-shaped or curved) isolation layer replaces conventional straight or rectangular isolation patterns. This curved geometry creates optimized electrical fields and current paths within the memory cell, improving device performance by reducing parasitic effects and enhancing charge storage efficiency in the capacitor structure.
Solution Approach 2:
The serpentine isolation layer serves multiple functions simultaneously: it defines the memory cell boundary, creates the source and drain regions through its geometry, provides electrical isolation, and establishes the spatial relationship between the transistor and capacitor components. This multi-functionality reduces the need for additional separate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the density of semiconductor devices, thereby improving their performance by optimizing the structure of memory cells, specifically DRAM cells, with an area density less than six times the square of the feature size per cell.
Implementation Method 1
The silicon nitride layer is removed to form a recess between the first polysilicon layer and the second polysilicon layer
Implementation Method 2
Exposed sidewalls of the first polysilicon layer and the second polysilicon layer are doped to define a source terminal contact and a drain terminal contact
Implementation Method 3
The concave portion is doped to define a channel region
Data Source
AI summary
The disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first and a second polysilicon layers on the substrate, a third polysilicon layer between the first and the second polysilicon layers, a first isolation layer adjacent with the first to the third polysilicon layers, a gate dielectric layer and a gate conductive layer in the third polysilicon layer, a second isolation layer on the gate conductive layer and the third polysilicon layer, a third isolation layer on the first the second isolation layers, a bit line via contact through the first and the third isolation layers, and a conductive layer on the bit line via contact and the third isolation layer. The third polysilicon layer has a concave portion between the first and the second polysilicon layers.