Serpentine Readout Architecture for SDM ADC Imagers
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Solution Overview
Problem
Current readout integrated circuits (ROICs) for strained layer superlattice (SLS) imagers face limitations in pixel size, signal-to-noise ratio, integration time, frame rate, bias voltage requirements, mechanical interface, and operating temperature, which constrain the design and performance of SLS sensors, particularly in infrared imaging applications.
Innovation Solution
The development of a readout integrated circuit (ROIC) utilizing sigma delta modulator (SDM) based analog-to-digital converters (ADCs) that employs a serpentine readout method to digitize the output of adjacent pixels, overcoming the spatial frequency bandwidth limitations of optical systems and reducing noise through oversampling and digital decimation filtering, while maintaining low power consumption and high resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ROIC designs are used for SLS imagers, then the design is constrained by pixel pitch, imager dimensions, well capacity, SNR, integration time, frame rate, bias voltage requirements, mechanical interface, and operating temperature, but using SDM ADCs with serpentine readout enables higher resolution and faster frame rates while maintaining low power consumption
Solution Approach 1:
The patent divides the imager array into multiple slices that are read out in parallel using separate SDM ADCs. Each slice is processed independently, allowing simultaneous readout of multiple pixels and enabling higher frame rates. The serpentine readout pattern further segments the reading process across time, reducing the complexity of timing control while maintaining high productivity.
Solution Approach 2:
The patent implements periodic sampling of pixel outputs using SDM ADCs with oversampling. The serpentine readout pattern creates a periodic sampling sequence that systematically visits each pixel in a time-varying manner. This periodic action enables high frame rates by efficiently cycling through all pixels in the array, while the digital decimation filtering processes the sampled data to achieve the desired resolution.
2Measurement precision
If SDM ADCs with oversampling are used to enhance signal-to-noise ratio, then resolution is improved, but the readout rate and processing complexity increase
Solution Approach 1:
The patent performs preliminary oversampling of the pixel outputs using SDM ADCs before the final digital processing stage. By acquiring multiple samples of each pixel output in advance, the system builds up the signal-to-noise ratio through averaging. The digital decimation filtering then processes these pre-sampled data to achieve the final high-resolution output, effectively separating the measurement precision function from the final processing step.
Solution Approach 2:
The patent changes the sampling rate parameter using SDM ADCs with variable oversampling ratios. By adjusting the oversampling rate, the system can enhance the signal-to-noise ratio for high-resolution applications while maintaining the ability to process data at high readout rates. The digital decimation filtering compensates for any rate variations, allowing flexible parameter optimization without sacrificing productivity.
3Measurement precision
If higher resolution is achieved through oversampling and digital decimation filtering, then image quality improves, but power consumption and processing requirements increase
Solution Approach 1:
The patent replaces traditional analog processing systems with digital signal processing using SDM ADCs. The oversampling and digital decimation filtering are performed in the digital domain rather than requiring complex analog circuits. This substitution reduces power consumption significantly while achieving higher resolution, as digital processing is more energy-efficient than analog processing for the same resolution requirements.
Solution Approach 2:
The patent optimizes the oversampling ratio parameter to achieve the desired resolution with minimal additional power consumption. By carefully selecting the oversampling rate, the system obtains sufficient signal-to-noise ratio improvement without excessive computational burden. The digital decimation filtering processes the data efficiently, maintaining low power consumption even at high resolutions.
Data Source
AI summary
The invention provides an imager readout architecture utilizing analog-to-digital converters (ADC), the architecture comprising a band-limited sigma delta modulator (SDM) ADC; and a serpentine readout, which can be configured to allow the band-limited SDM to multiplex between multiple columns by avoiding discontinuities at the edges of a row. SDM ADC image reconstruction artifacts are minimized using a modified serpentine read out methodology, the methodology comprising using primary and redundant slices with the serpentine read out in opposite directions and averaging the slices. Advantageously, the invention can be used to develop a read out integrated circuit (ROIC) for strained layer superlattice imagers (SLS) using sigma delta modulator (SDM) based analog to digital converters (SDM ADC).