Server on Chip Flow Pinning for Parallel Packet Processing
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Solution Overview
Problem
Traditional systems for processing Ethernet packet flows in server on a chip environments are costly, power-intensive, and inefficient due to the use of dedicated network interface cards, which process packets serially and lead to high latency and resource utilization.
Innovation Solution
A server on a chip system that extracts metadata from packets to associate them with specific cores of a multiprocessor, using a patricia tree and AVL search tree to enqueue packets in parallel queues, allowing simultaneous processing of multiple packet streams and reducing hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated network interface cards are used to process Ethernet packet flows, then packet processing reliability is improved, but system cost and power consumption increase significantly
Solution Approach 1:
The patent extracts the network interface card functionality from the traditional architecture and integrates it directly into the CPU cores. Each CPU core now has built-in Ethernet packet processing capability, eliminating the need for separate dedicated network interface cards while maintaining reliable packet processing.
Solution Approach 2:
The CPU cores are designed to perform multiple functions: they can execute general-purpose instructions and simultaneously handle Ethernet packet processing. This multi-functionality eliminates the need for dedicated network interface cards, reducing both cost and power consumption while maintaining processing reliability.
2Device complexity
If dedicated network interface cards process packets serially, then processing simplicity is maintained, but packet processing speed and throughput decrease
Solution Approach 1:
The patent segments the packet processing function across multiple CPU cores, with each core capable of independently processing packets. This parallel processing architecture dramatically increases throughput while maintaining relatively simple processing logic at each core level.
Solution Approach 2:
The patent transitions from serial processing (single dimension) to parallel processing across multiple CPU cores (adding another dimension). This dimensional change enables simultaneous processing of multiple packet streams, significantly improving speed and throughput.
3Ease of operation
If peripheral network interface cards enqueue packets to specific CPU queues, then flow management is simplified, but system latency increases
Solution Approach 1:
The patent removes the intermediate enqueuing step to peripheral network interface cards by integrating the queueing function directly into each CPU core. Packets are processed immediately when received, eliminating the latency introduced by peripheral enqueuing while maintaining flow management through direct core assignment.
4Reliability
If peripheral network interface cards are used, then Ethernet packet reception capability is ensured, but hardware cost and system real estate increase
Solution Approach 1:
The CPU cores are designed to perform multiple functions including Ethernet packet processing, eliminating the need for separate peripheral network interface cards. This integration reduces hardware cost and system real estate while ensuring reliable Ethernet packet reception capability through the multi-functional cores.
Data Source
AI summary
Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.