Server on Chip Flow Pinning for Parallel Packet Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional systems for processing Ethernet packet flows in computing networks are costly, power-intensive, and inefficient due to the use of dedicated network interface cards, which process packets serially and result in high latency and reduced system throughput.
Innovation Solution
A server on a chip that performs flow pinning by enqueuing packets to specific queues associated with each core in a multiprocessor system, allowing parallel processing of multiple packet streams from a single Ethernet interface, thereby increasing throughput and reducing hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated network interface cards are used to process Ethernet packet flows, then packet processing reliability is improved, but system cost and power consumption increase significantly
Solution Approach 1:
The patent combines the network interface functionality with the CPU by integrating multiple Ethernet interfaces directly into the processor chip. This merging eliminates the need for separate dedicated network interface cards, thereby reducing power consumption and system cost while maintaining packet processing reliability through the integrated design.
Solution Approach 2:
The processor is designed to perform multiple functions: it acts as both the central processing unit and the network interface controller. The integrated Ethernet interfaces can process packets from multiple sources simultaneously, making the processor universal in handling both general computing tasks and network packet processing, thus eliminating the need for specialized hardware.
2Device complexity
If dedicated network interface cards process packets serially, then processing simplicity is maintained, but system throughput decreases
Solution Approach 1:
The patent segments the packet processing function across multiple integrated Ethernet interfaces and multiple CPU cores. Each interface can handle specific packet streams independently, and multiple cores can process different flows in parallel. This segmentation enables simultaneous processing of multiple packet streams, dramatically increasing system throughput while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent transitions from serial processing to parallel processing by utilizing multiple CPU cores to handle different packet streams simultaneously. This adds a temporal dimension to packet processing, allowing multiple operations to occur concurrently rather than sequentially, thereby significantly improving system throughput.
3Adaptability or versatility
If peripheral network interface cards are used to enqueue packets to CPU queues, then packet routing flexibility is improved, but hardware cost and space increase
Solution Approach 1:
The patent merges the network interface card functionality with the CPU by integrating Ethernet interfaces directly into the processor. This integration eliminates the need for separate peripheral hardware, reducing the physical space required in the system while maintaining packet routing flexibility through software-based queue management and intelligent packet steering to appropriate CPU cores.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
A system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time.