Server Data Transmission via Peripheral Memory and BMC
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Solution Overview
Problem
Conventional data transmission within servers is inefficient, particularly due to the limitations of the low pin count (LPC) bus, which transmits data at a speed of 4 bytes per second, failing to meet the increasing demands for faster data transfer in modern applications.
Innovation Solution
The method involves a server architecture that includes a processor, main memory, southbridge, chipset, and peripheral memory, where the BIOS executes steps to obtain memory information for a peripheral controller, transmit data via the southbridge, and use a notifying command to store data in peripheral memory, enabling faster data transfer through the LPC bus by utilizing the PCIe standard and BMC access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted via the LPC bus using conventional BIOS methods, then compatibility with existing systems is maintained, but data transmission speed is limited to 4 bytes per second
Solution Approach 1:
The patent introduces peripheral memory as an intermediary component between the BIOS and BMC. Data is first transmitted from BIOS to peripheral memory at high speed via PCIe bus, then BMC retrieves data from peripheral memory. This intermediary approach enables the system to achieve high-speed data transmission while maintaining compatibility with existing LPC bus architecture.
Solution Approach 2:
The patent adds a new data transmission dimension by utilizing peripheral memory and PCIe bus interface, transitioning from the single-dimension LPC bus transmission. This creates a parallel high-speed transmission path that operates alongside the conventional LPC bus, effectively increasing overall data transmission capacity and speed without abandoning existing infrastructure.
2Productivity
If the LPC bus is used for data transmission, then system compatibility is maintained, but the transmission speed fails to meet modern application demands
Solution Approach 1:
The patent segments the data transmission process into two distinct phases: (1) high-speed data transfer from BIOS to peripheral memory via PCIe bus, and (2) data retrieval from peripheral memory to BMC via LPC bus. This segmentation allows each component to operate in its optimal performance mode, achieving high productivity while maintaining system compatibility through the LPC bus interface.
Solution Approach 2:
The patent performs preliminary data preparation by transmitting data from BIOS to peripheral memory before BMC needs to access it. This preliminary action utilizes the high-speed PCIe bus to pre-load data into peripheral memory, so that when BMC requires the data, it can be quickly retrieved without blocking the main transmission pipeline, thereby improving overall productivity while maintaining compatibility.
Data Source
AI summary
A method for data transmission within a server that includes a processor, a main memory, a southbridge, a chipset, and a buffer, the chipset including a baseboard management controller (BMC), the method including: obtaining memory information about a segment of the peripheral memory allocated for a peripheral controller included in the chipset; transmitting a notifying command to the BMC indicating a data size of to-be-transmitted data associated with a booting operation of the server; transmitting at least a part of the to-be-transmitted data to the segment, according to the memory information; and transmitting a standby command to the BMC indicating that the part of the to-be-transmitted data has been stored in the segment.