Server Delay Control Using Sleep-Polling and Interrupt Feedback

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Solution Overview

Problem

Existing packet transfer methods in server environments, such as interrupt and polling models, suffer from increased latency due to queuing and power consumption issues, particularly when CPU resources are contention or overloaded.

Innovation Solution

A server delay controller that monitors packet arrival using a polling model, includes a packet arrival monitoring unit, a packet harvesting unit, a sleep management unit, and a HW interrupt frequency control unit to manage CPU usage and reduce unnecessary hardware interrupts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a polling model is used to monitor packet arrival, then packet transfer delay is reduced, but CPU power consumption increases due to continuous monitoring

Engineering Contradiction:
Improvepacket transfer delayVSAvoidCPU power consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The polling thread operates periodically, alternating between sleeping and polling states. It polls packet arrival at intervals rather than continuously, reducing CPU power consumption while still achieving low packet transfer delay by waking up to check for packets and process them immediately when present

Inventive Principle:
Principle #19Periodic action

2Speed

If hardware interrupt is used for packet arrival notification, then packet transfer speed is improved, but latency increases due to interrupt queuing and scheduling

Engineering Contradiction:
Improvepacket transfer speedVSAvoidinterrupt latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent introduces a polling thread as an intermediary mechanism between the hardware interrupt and packet processing. Instead of directly responding to hardware interrupts which cause queuing and scheduling delays, the polling thread proactively checks for packet arrival and processes packets immediately when present, eliminating interrupt-related latency while maintaining high transfer speed

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If polling thread continuously monitors packet arrival, then packet transfer latency is minimized, but unnecessary CPU usage occurs when no packets are present

Engineering Contradiction:
Improvepacket transfer latencyVSAvoidCPU utilization efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The polling thread implements periodic monitoring by alternating between sleeping and polling states. It sleeps for a predetermined period when no packets are present, avoiding unnecessary CPU usage, and wakes up to poll for packet arrival, ensuring low latency is maintained only when packets are actually present to be processed

Inventive Principle:
Principle #19Periodic action

4Productivity

If hardware interrupt frequency is increased to handle high packet arrival rates, then packet processing capability is improved, but system stability deteriorates due to excessive interrupts

Engineering Contradiction:
Improvepacket processing capabilityVSAvoidsystem stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent implements feedback control by monitoring the hardware interrupt frequency and dynamically adjusting the polling interval. When interrupt frequency exceeds a threshold indicating excessive interrupts, the system increases the polling interval to reduce CPU workload and restore stability. When interrupt frequency is within acceptable range, the polling interval is decreased to improve packet processing capability, thus maintaining system stability while adapting to varying packet loads

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12498964B2Server delay control device, server delay control method and program
Publication Date: 2025.12.16 NT T INC
  • US12498964B2 patent drawing
  • US12498964B2 patent drawing
  • US12498964B2 patent drawing

AI summary

A server delay controller includes: a sleep management unit that makes a thread sleep when no packet arrives for a predetermined period and cancels the sleep of the thread with a hardware interrupt when the packet arrives; a HW interrupt frequency management table that stores the number of times of hardware interrupt; and a HW interrupt frequency control unit that calculates a HW interrupt frequency on the basis of the number of times of hardware interrupt and controls HW interrupt permission or prohibition by sleep of the sleep management unit on the basis of the calculated HW interrupt frequency.