Disaggregated Server IC Stack With Active Interposer Routing
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Solution Overview
Problem
Current semiconductor technologies face challenges with low vertical and horizontal interconnect density in modular server architectures, leading to decreased performance and increased manufacturing costs due to the use of solder-based connectivity and passive interposers.
Innovation Solution
A quasi-monolithic hierarchical integration architecture using recursively coupled IC dies with high-density interconnects, including a first and second layer of IC dies with conductive pathways and a third layer of router circuits, achieving silicon-level interconnect density and optimizing each die for specific functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If solder-based connectivity and passive interposers are used in modular server architectures, then ease of manufacture is improved, but interconnect density and performance deteriorate
Solution Approach 1:
An active interposer die is introduced as an intermediary component between compute dies and memory dies. This active interposer contains router circuits that actively manage data flow, replacing the passive interposer approach. The active interposer provides high-density interconnects while maintaining manufacturability through standardized interfaces and automated assembly processes.
Solution Approach 2:
The system is segmented into distinct functional modules: compute dies, memory dies, and an active interposer die. Each module is independently fabricated and optimized for its specific function, then assembled through automated packaging. This segmentation allows each component to achieve high manufacturing precision while maintaining overall ease of manufacture through modular assembly.
2Manufacturing precision
If vertically stacked IC dies are used to increase interconnect density, then interconnect density is improved, but manufacturing complexity increases
Solution Approach 1:
The architecture transitions from two-dimensional planar interconnection to three-dimensional vertical stacking. Multiple layers of IC dies are stacked vertically with high-density interconnects providing connections between layers. This dimensional change enables significantly higher interconnect density while managing complexity through standardized vertical interfaces and automated stacking processes.
Solution Approach 2:
The vertically stacked architecture implements a nested structure where compute dies, memory dies, and router dies are arranged in multiple hierarchical layers. Each layer is self-contained with specific functionality, and layers are nested vertically to create a compact three-dimensional structure. This nesting approach maximizes interconnect density while managing device complexity through modular layer design.
Data Source
AI summary
A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.