Multi-Node Server Mainboard I2C Monitoring and Clock Architecture
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Solution Overview
Problem
In server systems with a high number of PCIE devices, address conflicts and prolonged I2C polling durations occur, leading to delayed monitoring of device information, and the reliance on CPU and PCH for clock signals results in resource waste and dependency issues, preventing independent operation of devices.
Innovation Solution
A flexibly configured multi-computation-node server mainboard structure with a processing unit connected to PCIE devices via I2C buses, analyzing data for abnormalities, and independently providing clock signals to devices, allowing for concurrent data acquisition, immediate abnormality reporting, and reduced resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If BMC uses I2C buses to connect to PCIE devices for monitoring, then device information can be acquired, but address conflicts occur when an excessively high quantity of PCIE devices are installed
Solution Approach 1:
The patent divides the I2C monitoring system into multiple I2C switches (first I2C switch, second I2C switch, etc.), each managing a subset of PCIE devices. This segmentation allows the system to support a larger quantity of PCIE devices without address conflicts, as each switch provides its own address space for connected devices.
2Quantity of substance
If BMC polls all PCIE devices through I2C buses, then device information is monitored, but the polling duration becomes excessively long when devices are too many
Solution Approach 1:
The patent segments the polling process by having BMC poll only the I2C switches rather than individually polling each PCIE device. The I2C switches aggregate device information and present it to BMC, significantly reducing the polling duration while still enabling monitoring of a large quantity of devices.
Solution Approach 2:
The I2C switches act as intermediaries between BMC and PCIE devices. They collect information from multiple devices and present aggregated data to BMC, reducing the time BMC spends polling while maintaining comprehensive device monitoring capability.
3Reliability
If PCIE devices use PCH or CLOCK BUFFER for clock signals, then clock signals can be provided, but devices cannot operate independently when CPU or PCH is abnormal
Solution Approach 1:
The patent equips each PCIE device with its own independent clock signal generation capability through integrated clock modules. This local quality ensures that each device can operate independently without relying on CPU or PCH, improving system reliability while the clock modules integrate seamlessly into the existing device architecture.
4Reliability
If CPU and PCH are used to provide clock signals to PCIE devices, then clock signals are available, but resource utilization ratios are very low causing cost waste
Solution Approach 1:
The patent enables PCIE devices to generate their own clock signals through integrated clock modules, making them self-sufficient. This eliminates the need for CPU and PCH to continuously provide clock signals, reducing resource waste and improving energy efficiency while ensuring reliable clock signal availability.
Data Source
AI summary
A flexibly configured multi-computing-node server mainboard structure and a method. A processing unit connects to PCIE devices via I2C concurrently. The processing unit analyzes whether the acquired data of the PCIE devices are abnormal. The processing unit connects to a baseboard management controller via I2C, when the data are normal, the processing unit polls to transmit analyzed data to the baseboard management controller via I2C. When the data are abnormal, the processing unit pauses polling and transmitting information, and preferentially transmits abnormality information to the baseboard management controller. The processing unit is provided with an internal clock assembly and an external clock assembly, the external clock assembly is connected to a PCH, the internal clock assembly and the external clock module are connected to a data selector, and an output of the data selector is electrically connected to the PCIE devices.