Server Memory Error Logging via BMC Threshold Aggregation

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Solution Overview

Problem

Conventional server computers with ECC memory face resource and performance issues due to frequent detection and recording of memory errors, leading to increased CPU time in System Management Mode and resource consumption.

Innovation Solution

A method where a processing module in a server computer determines if a correctable memory error count exceeds a predetermined value before sending update event information to the BMC for recording, thereby optimizing resource usage and reducing unnecessary error logging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the CPU frequently sends and records error information for the same memory error, then complete error logging is achieved, but system resources (CPU and storage) are heavily consumed

Engineering Contradiction:

Improveerror logging completenessVSAvoidsystem resource consumption

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent introduces a memory controller as an intermediary between the CPU and BMC. The memory controller aggregates multiple correctable memory errors and only notifies the BMC when the error count reaches a threshold, thereby reducing the frequency of CPU-BMC communications and lowering system resource consumption while still maintaining error logging functionality

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of logging every single correctable error, the patent implements partial logging by only recording errors when their cumulative count exceeds a predetermined threshold. This selective approach reduces the volume of logged data and associated resource usage while still capturing significant error patterns

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If the CPU frequently enters System Management Mode to handle memory errors, then error correction is achieved, but OS execution thread stability is compromised

Engineering Contradiction:

Improveerror correction capabilityVSAvoidCPU time in SMM

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by having the CPU enter SMM only when the aggregated error count reaches a threshold, rather than entering SMM for every single correctable error. This reduces the frequency of SMM transitions and minimizes interference with OS execution threads while still maintaining error correction capability

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The memory controller performs preliminary error aggregation and counting before triggering SMM. By pre-processing error data and only escalating when necessary, the system avoids frequent SMM entries and their associated performance penalties

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11182233B2Method for event log management of memory errors and server computer utilizing the same

Publication Date: 2021.11.23 MITAC COMPUTING TECH

AI summary

A method for recording memory errors includes the following steps: upon detecting a current correctable error that occurred in a volatile memory device, determining whether a count value corresponding to the current correctable error exceeds a predetermined value; and when it is determined that the count value corresponding to the current correctable error thus detected does not exceed the predetermined value, sending update event information corresponding to the current correctable error to a BMC, in order for the BMC to record information of the current correctable error.