Server Memory Synchronization via PCIE Switch Interconnect
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Solution Overview
Problem
Conventional cluster systems waste approximately 20% of data transmission bandwidth due to the use of 10G NICs and packet conversion when synchronizing memory data between motherboards.
Innovation Solution
The system directly interconnects redundant motherboards using PCIE switch chips to transmit synchronization data, eliminating the need for NICs and packet conversion, thereby reducing bandwidth consumption and minimizing network conversion delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NIC with 10G and packet conversion are used for memory data synchronization, then data transmission capability is improved, but bandwidth consumption increases by approximately 20%
Solution Approach 1:
The patent extracts and removes the NIC and packet conversion layers from the data transmission path. By using PCIE switch chips to directly interconnect motherboards, the system eliminates the need for network protocol packaging and unpackaging, thereby removing the source of the 20% bandwidth waste while maintaining high-speed data transmission capability.
Solution Approach 2:
Instead of converting PCIE packet data to network packet data through NIC (the conventional approach), the patent inverts the approach by using PCIE switch chips that natively handle PCIE packet data without conversion. This reverses the traditional network-based synchronization architecture to a direct PCIE-based architecture, eliminating the conversion overhead.
2Speed
If NIC with 10G is disposed in each motherboard for data synchronization, then transmission bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent merges the data transmission function into the existing PCIE interface infrastructure. By using PCIE switch chips that are already integrated into the motherboard architecture, the system combines memory data synchronization with the existing PCIE data transmission pathway, eliminating the need for separate NIC hardware and reducing overall device complexity.
Solution Approach 2:
The PCIE switch chips serve multiple functions: they handle both general PCIE data transmission and memory data synchronization tasks. This multi-functionality eliminates the need for dedicated NIC hardware, as the PCIE switch chips can be configured to perform synchronization operations without requiring additional specialized components.
3Adaptability or versatility
If packet conversion is performed between PCIE packet data and network packet data, then data transmission compatibility is improved, but transmission efficiency deteriorates due to bandwidth waste
Solution Approach 1:
The patent introduces PCIE switch chips as intermediaries between motherboards for memory data synchronization. These switch chips natively understand and handle PCIE packet data format, eliminating the need to convert to network packet data format. The intermediary maintains compatibility through the standard PCIE protocol while avoiding the inefficient network packet conversion process.
Data Source
AI summary
A server system is described. The server system comprises first motherboard having first processor module coupled to first memory module, second motherboard having second processor module coupled to second memory module, first back plate having first PCIE switch chip coupled to second PCIE switch chip via PCIE transmission channel. The first processor module is coupled to the first PCIE switch chip and the second processor module is coupled to the second PCIE switch chip. The first processor module converts the memory data of the first memory module into PCIE packet data to be transmitted to the second processor module by first PCIE switch chip and second PCIE switch chip. The second processor module converts the received PCIE packet data into memory data of second memory module for synchronizing the memory data of first motherboard and the second motherboard.