Server NIC Switching for Power Efficiency

The patent applies dynamics by making the packet processing path selectable between FPGA and CPU based on traffic load conditions. The system dynamically switches between hardware acceleration mode (FPGA) for high load and software processing mode (CPU) for low load, allowing the architecture to adapt its state rather than remaining fixed. This resolves the contradiction by enabling the system to achieve high processing performance when needed while avoiding wasted power consumption during low-activity periods.

The patent applies parameter changes by monitoring traffic amount as a key parameter and using this information to change the processing mode. When traffic amount exceeds a threshold, the system switches to FPGA processing to enhance capability; when traffic amount falls below the threshold, it switches to CPU processing to reduce power consumption. This dynamic parameter-based switching resolves the contradiction between processing capability and power consumption by aligning resource allocation with actual demand.

The patent applies universality by enabling a single server to perform multiple processing functions through flexible path selection. The server can dynamically choose between FPGA-based hardware acceleration and CPU-based software processing, effectively making one server capable of handling varying workloads that would traditionally require multiple dedicated servers. This multi-functional capability resolves the contradiction by eliminating the need for proportional scaling of hardware resources while maintaining processing performance.