Server NVMe Bridge Board Architecture for Bandwidth and Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern server interfaces, such as SAS and NL-SAS, face insufficient bandwidth and high latency issues when connected to solid state disks or phase change memory, and direct PCIE interface connections can be cumbersome due to wiring constraints.
Innovation Solution
A server design featuring a main board that provides NVME data signals, a bridge board that processes and distributes these signals to sub boards with storage modules, and a control mechanism to monitor storage module status, utilizing a PCIE standard bus for efficient data transmission and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If SAS or NL-SAS interfaces are used for connecting storage devices, then compatibility and ease of operation are improved, but bandwidth is insufficient and latency increases
Solution Approach 1:
The system segments the interface architecture into multiple layers: the main board provides NVME data signals, the bridge board processes and distributes these signals to multiple sub boards, and each sub board connects to storage modules. This segmentation allows the system to utilize high-bandwidth NVME interfaces while maintaining compatibility with existing storage devices through the bridge board's signal conversion capabilities.
Solution Approach 2:
The bridge board acts as an intermediary between the NVME interface and traditional SAS/NL-SAS storage devices. It receives high-speed NVME data signals from the main board, processes and converts them, and distributes them to sub boards that connect to storage modules. This intermediary approach enables the system to achieve high bandwidth through NVME while maintaining compatibility with existing storage interfaces.
2Productivity
If PCIE interface card is directly connected to main board, then bandwidth and speed are improved, but wiring complexity and device complexity increase
Solution Approach 1:
The system divides the PCIE interface functionality into separate modules: the main board provides NVME data signals through its own PCIE interface, while the bridge board and sub boards handle signal distribution and storage module connections. This segmentation reduces wiring complexity on the main board while maintaining high data transmission speeds through the distributed architecture.
Solution Approach 2:
The bridge board serves as an intermediary that receives NVME data signals from the main board and distributes them to multiple sub boards. This intermediary approach simplifies the main board's wiring requirements while enabling high-speed data transmission to multiple storage modules through the distributed sub board architecture.
3Ease of operation
If multiple storage modules are connected through traditional interfaces, then ease of operation is maintained, but latency increases and parallel access capability is limited
Solution Approach 1:
The system segments the storage connection architecture into multiple independent sub boards, each capable of parallel access to storage modules. The bridge board distributes NVME data signals to these sub boards, enabling simultaneous data access across multiple storage modules. This segmentation reduces access latency by allowing parallel operations while maintaining ease of operation through standardized connection interfaces.
Solution Approach 2:
The NVME interface enables continuous data transmission between the main board, bridge board, and sub boards without the latency interruptions characteristic of traditional SAS/NL-SAS interfaces. The pipeline architecture allows multiple data operations to proceed simultaneously across different sub boards and storage modules, eliminating idle time and maintaining continuous useful action throughout the data access process.
Data Source
AI summary
A server includes a main board, a bridge board and sub boards. The bridge board is electrically connected to the main board and the sub boards. The main board provides a data signal according to a transmission format of non-volatile memory express (NVME). The bridge board obtains the data signal according to the transmission format of NVME. The bridge board produces sub data signals according to the data signal or the transmission format of NVME. One of the sub boards obtains one of the sub data signals according to the transmission format of NVME. The bridge board instructs with one of the sub boards to detect the storage module in the sub board to produce at least one status parameter or produce at least one mode determination result.