Service Chaining Hardware Accelerators in Data Stream Processing ICs
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Solution Overview
Problem
Current general-purpose processors in data centers are inefficient for high-capacity network and storage workloads due to their poor performance in processing packet streams.
Innovation Solution
The implementation of a data processing unit (DPU) with hardware-based accelerators and a multiple core processor system that uses a work unit stack data structure to manage and execute service chains of operations, enabling efficient processing of stream data units through parallel and pipelined processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If general purpose processors are used to process network data, then device versatility is maintained, but processing speed and throughput deteriorate
Solution Approach 1:
The processor is segmented into general purpose cores and specialized hardware accelerators. The general purpose cores handle control plane functions and complex packet processing, while hardware accelerators handle specific high-speed operations like encryption, compression, and protocol processing. This segmentation allows each component to be optimized for its specific function while maintaining overall system versatility.
Solution Approach 2:
The system achieves universality through a hybrid architecture where general purpose cores can handle any processing task, while hardware accelerators provide specialized functionality. The control plane software dynamically allocates work between cores and accelerators based on packet type and processing requirements, ensuring the system can adapt to various network protocols and applications while maintaining high performance for specific operations.
2Productivity
If multiple hardware accelerators are integrated into DPU, then processing throughput is improved, but device complexity increases
Solution Approach 1:
Multiple hardware accelerators are merged into a single integrated DPU device, sharing common resources such as memory, interconnect fabric, and control logic. This consolidation improves throughput by enabling parallel processing of different packet streams simultaneously while managing complexity through shared infrastructure rather than separate standalone devices.
Solution Approach 2:
A control plane processor and software layer act as intermediaries between the general purpose cores and hardware accelerators. This intermediary manages the complexity of coordinating multiple accelerators by providing a unified interface, resource allocation, and task scheduling, thereby enabling high throughput without requiring direct complex interactions between all accelerator components.
3Productivity
If hardware accelerators perform specific operations, then processing efficiency is improved, but programming complexity increases
Solution Approach 1:
The control plane software provides a universal programming interface that abstracts the complexity of hardware accelerators. Developers can program the DPU using high-level constructs that automatically map to appropriate hardware accelerators based on operation type, eliminating the need for developers to directly program each accelerator's specific interface while maintaining high processing efficiency.
Solution Approach 2:
The system implements self-service through automatic work unit generation and accelerator selection. The control plane software automatically generates work units from high-level programming constructs and selects the most appropriate hardware accelerator for each operation based on the task requirements, thereby improving efficiency while reducing programming complexity through automation.
Data Source
AI summary
This disclosure describes techniques that include establishing a service chain of operations that are performed on a network packet as a sequence of operations. In one example, this disclosure describes a method that includes storing, by a data processing unit integrated circuit, a plurality of work unit frames in a work unit stack representing a plurality of service chain operations, including a first service chain operation, a second service chain operation, and a third service chain operation; executing, by the data processing unit integrated circuit, the first service chain operation, wherein executing the first service chain operation generates operation data; determining, by the data processing unit integrated circuit and based on the operation data, whether to perform the second service chain operation; and executing, by the data processing unit integrated circuit, the third service chain operation after skipping the second service chain operation.