Service Layer Adapter for Lowest Point of Coherency Memory Management
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Solution Overview
Problem
Current computer systems face challenges in efficiently managing lowest point of coherency (LPC) memory, particularly in symmetric multi-processing environments, where memory access instructions require translation and coherency maintenance across different memory locations, leading to latency and complexity.
Innovation Solution
A service layer adapter is employed, coupled with a processor and an accelerator, to receive memory access instructions, translate effective addresses to real addresses, and direct memory access requests between LPC memory and other memory locations, using base address registers and a media controller, thereby optimizing memory access and coherency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory access instructions are translated and coherency is maintained across different memory locations in symmetric multi-processing environments, then memory access correctness is ensured, but latency increases and access efficiency decreases
Solution Approach 1:
The patent segments memory into coherent memory regions and non-coherent LPC memory regions, allowing different access handling strategies for each segment. This enables fast direct access to LPC memory while maintaining coherency protocols only where necessary, thus reducing overall latency while preserving correctness.
Solution Approach 2:
The patent introduces a memory management unit (MMU) and translation lookaside buffer (TLB) as intermediary components between the processor and memory. These intermediaries handle address translation and coherency management, offloading this overhead from the main memory access path and reducing latency for LPC memory accesses.
2Reliability
If address translation and coherency management are performed for all memory access requests, then memory integrity is maintained, but device complexity increases
Solution Approach 1:
The patent applies different quality levels of memory management to different memory regions. LPC memory regions use simplified access paths with minimal coherency checking, while other memory regions use full coherency protocols. This localized approach maintains integrity where needed while reducing complexity for LPC memory.
Solution Approach 2:
The patent implements dynamic memory attribute setting where memory regions can be configured as coherent or non-coherent based on their usage requirements. This dynamic configuration allows the system to adapt memory management complexity to actual needs, reducing overall system complexity while maintaining integrity for critical regions.
3Reliability
If LPC memory is accessed through the coherent interface, then coherency is maintained, but storage access efficiency decreases
Solution Approach 1:
The patent inverts the traditional approach by providing a dedicated non-coherent access path for LPC memory while maintaining a separate coherent path for other memory. This inversion allows LPC memory to be accessed efficiently through the optimized path while coherency is maintained through the alternative path when needed.
Solution Approach 2:
The patent creates a universal memory access architecture that can handle both coherent and non-coherent memory types through a unified interface. The MMU and memory controller can dynamically route accesses through appropriate paths, providing multi-functionality that supports both efficiency and coherency requirements.
Data Source
AI summary
Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.