Service Processor Debugging Microprocessor Reset Events

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Solution Overview

Problem

The existing microprocessor debugging and performance tuning tools, such as the tracer, are disruptive to the normal processor state and can only run during instruction execution, limiting their effectiveness in capturing asynchronous events and potentially affecting processor performance.

Innovation Solution

A microprocessor integrated circuit with a service processor (SPROC) that detects asynchronous events and resets the main processor, allowing microcode to read and output debug information on external buses, enabling non-intrusive logging and action execution independent of instruction execution boundaries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If tracer microcode is activated to debug and performance tune the processor, then processor state information can be captured, but the processor state changes from normal operation which may reduce tracer's usefulness and affect processor performance

Engineering Contradiction:
Improvedebugging accuracyVSAvoidprocessor state integrity
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces a service processor as an intermediary component that runs independently from the main processor. The service processor executes debug and performance tuning operations without directly interfering with the main processor's instruction execution, thereby capturing processor state information while minimizing disruption to normal processor operation and state integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of information

If tracer microcode is used to capture processor state information, then debugging information can be obtained, but tracer can only run during instruction execution which limits capturing asynchronous events

Engineering Contradiction:
Improvedebug information completenessVSAvoidevent detection capability
Core Design Contradiction:
Loss of informationVSAdaptability or versatility

Solution Approach 1:

The patent segments the processing functions by separating the service processor from the main processor. The service processor handles asynchronous event detection and debugging operations independently, while the main processor focuses on instruction execution. This segmentation allows asynchronous events to be captured without requiring the main processor to be in a specific instruction execution state.

Inventive Principle:
Principle #1Segmentation

3Productivity

If tracer is implemented as microcode instructions within the processor, then it can execute during instruction processing, but it disrupts the normal processor state that is created by the program being debugged

Engineering Contradiction:
Improvedebugging efficiencyVSAvoidprocessor operation normality
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The service processor acts as an intermediary that handles debugging and performance tuning tasks without directly interfering with the main processor's normal operation. This allows debugging activities to proceed efficiently while maintaining the normality of processor operations being debugged.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Loss of information

If the processor resets during debugging to capture state information, then debug information can be output, but the reset may cause loss of debug information if not properly managed

Engineering Contradiction:
Improvedebug information retentionVSAvoidreset operation safety
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The service processor performs preliminary actions by capturing and storing processor state information in internal memory before a reset occurs. This ensures that debug information is preserved and can be output after the reset without loss, making the reset operation safe for debugging purposes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8464032B2Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit
Publication Date: 2013.06.11 VIA TECH INC
  • US8464032B2 patent drawing
  • US8464032B2 patent drawing
  • US8464032B2 patent drawing

AI summary

A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor.