Service Processor Memory Checkpointing via Segmented Bus Architecture
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Solution Overview
Problem
Existing computer systems face challenges in efficiently recovering memory checkpoints during failures due to shared resource conflicts and data latency issues in service processor and CPU interactions, particularly in split memory bus architectures.
Innovation Solution
A local service processor with an alternative power supply and network interface is employed to access and mimic the memory controller, enabling independent memory operations and checkpointing, which includes periodic status checks and data transfer to a new node in case of failure, using either a split or service memory bus architecture, or 3D stacked memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared memory bus architecture is used for CPU and service processor interactions, then device complexity is reduced, but data latency increases during failure recovery operations
Solution Approach 1:
The patent segments the memory access path by providing the service processor with direct access to memory through its own interface, separate from the CPU's memory bus. This segmentation allows the service processor to access memory independently without contending with CPU memory operations, thereby reducing data latency during failure recovery while maintaining architectural simplicity.
2Device complexity
If the service processor shares power supply with the CPU, then device complexity is reduced, but reliability decreases during system failures
Solution Approach 1:
The patent extracts the power supply function from the shared CPU power source and provides the service processor with an alternative, independent power supply. This extraction ensures that during CPU failures, the service processor remains powered and operational, enabling it to perform failure detection and memory checkpoint recovery operations independently of the failed CPU.
3Device complexity
If the service processor has limited memory access capability, then device complexity is reduced, but productivity decreases during checkpoint recovery operations
Solution Approach 1:
The patent implements preliminary action by having the service processor periodically access memory to detect CPU status and initiate failure recovery operations before the CPU fully fails. The service processor can proactively monitor system health, detect early signs of failure, and begin checkpoint recovery operations in advance, thereby improving recovery productivity while maintaining simple service processor design.
Data Source
AI summary
A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.