SET Filtered Sequential Circuit for Radiation-Hardened Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS integrated circuits are vulnerable to radiation effects such as Single Event Effects (SEE) and Single Event Transients (SET), which can cause logic errors and data corruption, especially in aerospace and military applications, and existing mitigation techniques often require significant silicon area or complex circuit designs.
Innovation Solution
The implementation of a SET filter and SEU mitigated sequential element circuit that generates three nominally equivalent data channels, which are transmitted separately to three sequential elements, using a combination of delay elements and guard gates to filter out transient signals and ensure correct logic states, thereby providing a complete SEE hardened solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SET mitigation techniques are used, then radiation reliability is improved, but silicon area and circuit complexity increase significantly
Solution Approach 1:
The circuit is segmented into three nominally equivalent data channels that are processed independently through separate sequential elements. This segmentation allows the system to handle SET events in one channel without affecting the others, improving radiation reliability while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent creates three copies of the data path (nominally equivalent data channels) to provide redundancy against SET events. By copying the logic and processing identical data through multiple independent paths, the system achieves radiation hardening without requiring entirely new complex mitigation architectures
2Reliability
If driver size is increased to mitigate SEU, then logic error resistance is improved, but transistor size and silicon area increase
Solution Approach 1:
Rather than uniformly increasing driver size throughout the circuit, the patent applies local quality by making drivers sufficiently sized only where needed to counteract field funnel effects in specific vulnerable regions, while using other mitigation techniques in less vulnerable areas, thus optimizing the balance between logic error resistance and transistor area
3Reliability
If feedback path extension is used for SEU mitigation, then logic error recovery is improved, but circuit complexity and silicon area increase
Solution Approach 1:
The feedback path is segmented into multiple independent sequential elements, each with its own feedback loop. This allows the circuit to recover from logic errors locally in affected segments without requiring extensive modifications to the entire feedback structure, maintaining simpler overall circuit complexity while improving logic error recovery
4Reliability
If multiple nominally equivalent data channels are generated, then SET filtering effectiveness is improved, but circuit complexity increases
Solution Approach 1:
The patent merges multiple nominally equivalent data channels at the output stage, combining the results from three independent processing paths. This merging approach achieves effective SET filtering by requiring consensus among multiple channels while avoiding the need for complex individual filtering circuits in each path, thus improving SET filtering effectiveness without proportionally increasing circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates both SET and SEU events, providing a robust solution for radiation-hardened integrated circuits without the need for extensive silicon area or complex designs, ensuring reliable operation in radiation environments.
Implementation Method 1
a delay element having an input coupled to receive the first logic signal and an output for providing a second logic signal that is a delayed version of the first logic signal
Implementation Method 2
a guard gate having a first input coupled to receive the first logic signal, a second input coupled to receive the second logic signal, and an output for providing a third logic signal
Implementation Method 3
generates three nominally equivalent data channels, which are transmitted separately to three sequential elements
Data Source
AI summary
A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.