SET Filtering Circuit for Radiation-Hardened Sequential Logic
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Solution Overview
Problem
CMOS integrated circuits are vulnerable to radiation effects such as Single Event Effects (SEE) and Single Event Transients (SET) in aerospace and military applications, which current mitigation techniques struggle to address effectively, especially in commercial ASICs and PLDs, where silicon area is a concern and radiation hardening is not readily available.
Innovation Solution
The implementation of a SET filter and SEU mitigated sequential element circuit that generates three nominally equivalent data channels, transmitted separately to three sequential elements, using a combination of delay elements and guard gates to filter out transient signals and ensure correct logic states, thereby providing a comprehensive solution for SEE hardening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SEU mitigation techniques (such as making node drivers large or using dice-cell structures) are used, then reliability against radiation effects is improved, but silicon area increases significantly
Solution Approach 1:
The patent segments the data path into three separate nominally equivalent data channels that are transmitted separately to three sequential elements. This segmentation allows the system to process data through multiple independent paths, reducing the vulnerability to single event effects while maintaining compact circuit area through shared infrastructure.
Solution Approach 2:
The patent applies radiation mitigation selectively at critical points in the circuit (at the sequential elements receiving data channels) rather than throughout the entire circuit. The guard gates and delay elements are positioned locally at decision points, providing targeted protection without requiring comprehensive area expansion across the whole circuit.
2Reliability
If SET filter circuits are added to mitigate single event transients, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements delay elements that hold the logic signal for a predetermined time period before it reaches the sequential element. This preliminary action occurs before the potential harmful transient can affect the circuit state, allowing the system to naturally filter out short-duration transients without requiring complex active filtering circuits.
Solution Approach 2:
The patent introduces guard gates as intermediary components between the data channels and the sequential elements. These guard gates act as mediators that monitor the logic signals and only allow valid transitions to propagate, blocking transient-induced false transitions while maintaining the simplicity of the overall circuit architecture.
3Reliability
If three separate data channels are transmitted to three sequential elements, then mitigation of both SET and SEU is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent designs the three nominally equivalent data channels to share common infrastructure components such as delay elements, guard gates, and sequential elements. This multi-functional approach allows the same circuit blocks to serve multiple purposes across different data channels, simplifying the manufacturing process while achieving comprehensive SEE hardening through redundant processing paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates both SET and SEU events, providing a complete SEE hardened solution for CMOS integrated circuits, enhancing their reliability in radiation environments without significant increases in silicon area, and can be applied to entire designs by replacing sequential elements.
Implementation Method 1
a delay element that delays a logic signal for a predetermined time period
Implementation Method 2
a guard gate that filters logic signals based on timing
Implementation Method 3
generates three nominally equivalent data channels, transmitted separately to three sequential elements
Data Source
AI summary
A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.