SET Mitigation Circuit With Localized Transistor Upsizing
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Solution Overview
Problem
Existing Radiation-Hardened-By-Design (RHBD) techniques for mitigating Single-Event-Transients (SETs) in integrated circuits (ICs) suffer from high overheads in terms of power dissipation, silicon area, and delay, limiting their application to only those that can tolerate such overheads.
Innovation Solution
A circuit design that mitigates SETs by using a sub-circuit configuration with p-type and n-type transistor arrangements connected in series, reducing overheads while maintaining robustness against SETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor up-sizing is used to suppress SETs, then SET suppression capability is improved, but power dissipation and silicon area increase significantly
Solution Approach 1:
The circuit is divided into two sub-circuits: a first sub-circuit with standard-sized transistors for normal operation, and a second sub-circuit with up-sized transistors specifically for SET suppression. This segmentation allows only the necessary portion of the circuit to have enhanced SET immunity, reducing overall power dissipation and area overhead compared to upsizing the entire circuit.
Solution Approach 2:
The up-sized transistors are placed locally at the output node where SET suppression is most critical, rather than upsizing all transistors in the circuit. This localized approach concentrates the SET mitigation capability where it is needed most while minimizing the impact on power dissipation and silicon area.
2Reliability
If transistor up-sizing is used to suppress SETs, then SET suppression capability is improved, but silicon area increases significantly
Solution Approach 1:
The circuit is divided into two sub-circuits: a first sub-circuit with standard-sized transistors for normal operation, and a second sub-circuit with up-sized transistors specifically for SET suppression. This segmentation allows only the necessary portion of the circuit to have enhanced SET immunity, reducing overall power dissipation and area overhead compared to upsizing the entire circuit.
Solution Approach 2:
The up-sized transistors are placed locally at the output node where SET suppression is most critical, rather than upsizing all transistors in the circuit. This localized approach concentrates the SET mitigation capability where it is needed most while minimizing the impact on power dissipation and silicon area.
3Reliability
If complex RHBD design techniques are used, then SET mitigation is improved, but device complexity increases
Solution Approach 1:
The circuit is divided into two sub-circuits: a first sub-circuit with standard-sized transistors for normal operation, and a second sub-circuit with up-sized transistors specifically for SET suppression. This segmentation allows only the necessary portion of the circuit to have enhanced SET immunity, reducing overall power dissipation and area overhead compared to upsizing the entire circuit.
Solution Approach 2:
The two sub-circuits are merged such that the output of the first sub-circuit is electrically coupled to the input of the second sub-circuit, and their outputs are electrically coupled together. This merging allows the standard-sized and up-sized transistor arrangements to work together, achieving SET mitigation with reduced overall complexity compared to using only complex RHBD techniques throughout the entire circuit.
Data Source
AI summary
A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to generate a second output; and a second sub-circuit comprising a connecting p-type transistor arrangement and a connecting n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other through the second sub-circuit.