SET Pulse Measuring Circuit With Dual-Chain Error Elimination
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Solution Overview
Problem
Existing SET pulse measuring circuits in anti-irradiation test chips generate extra SET pulses when exposed to irradiation, leading to deviations in experimental results from actual anti-irradiation performance, due to the circuit's exposure and increased clock frequency.
Innovation Solution
A SET pulse measuring circuit design that includes a test chain of cascaded inverters, latch circuits to store node information, a flip-flop test circuit for serial output, and a latching self-trigger circuit to generate a HOLD signal, allowing for the elimination of extra SET pulses by distinguishing between externally generated and internally generated pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the measuring circuit is exposed to the irradiation environment to measure SET pulses, then the measurement function is achieved, but extra SET pulses are generated by the measuring circuit itself, causing measurement deviation
Solution Approach 1:
The patent divides the measuring circuit into two identical independent sets (first measuring circuit and second measuring circuit), each capable of independent measurement. By comparing results from both circuits, the system can identify and eliminate measurements affected by extra SET pulses generated within the measuring circuits themselves, thereby improving measurement precision while accounting for the harmful effect of extra pulses.
Solution Approach 2:
The patent creates a copy of the measuring circuit (second measuring circuit as a copy of the first) to perform redundant measurements. This copying approach allows the system to distinguish between genuine SET pulses from the device under test and spurious pulses generated by the measuring circuit, by comparing whether both copies produce identical results.
2Productivity
If the clock frequency is increased to improve measurement speed, then productivity is improved, but the frequency of extra SET pulses generated by the measuring circuit increases
Solution Approach 1:
The patent implements a feedback mechanism where the results from both measuring circuits are compared. When the outputs differ, it indicates the presence of extra SET pulses, and the system can identify which measurement is affected. This feedback loop allows the system to maintain high clock frequencies for productivity while automatically correcting for the increased frequency of harmful extra pulses through comparative validation.
3Volume of moving object
If the process size is reduced to improve integration, then device miniaturization is achieved, but the circuit becomes more susceptible to radiation effects and generates more extra SET pulses
Solution Approach 1:
The patent changes the parameter of measuring circuit configuration from a single circuit to dual identical circuits. This parameter change allows the system to maintain miniaturized process sizes while compensating for increased radiation susceptibility through redundant measurement and comparison, effectively filtering out extra SET pulses generated by the smaller, more vulnerable circuits.
Data Source
AI summary
The present disclosure discloses a Single-Event Transient (SET) pulse measuring circuit capable of eliminating impact thereof, and an integrated circuit chip. The SET pulse measuring circuit capable of eliminating impact thereof includes four parts: a SET pulse test chain, a latch circuit, a flip-flop test circuit, a latching self-trigger circuit. The integrated circuit chip is provided with a test chain module and two sets of SET pulse measuring circuits capable of eliminating impact thereof, and inputs of the two sets of SET pulse measuring circuits capable of eliminating impact thereof are the same and each are connected to an output terminal of the test chain module.