Edge-Triggered Set-Reset Circuit for Adaptive Clock Jitter Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computing designs face issues with timing errors and power dissipation due to substantial voltage transients, leading to increased power consumption and reduced performance, particularly in adaptive clocking systems where extraneous jitter is a significant problem.
Innovation Solution
A circuit and method that utilize an edge-sensitive reset-set (RS) latch and adaptive window synchronization to generate accurate set and reset signals, reducing voltage margins and power dissipation by automatically adjusting the clock frequency in response to voltage droops, thereby minimizing the impact of transient voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional computing circuitry operates at higher voltage to maintain timing accuracy during voltage transients, then timing accuracy is improved, but power dissipation increases
Solution Approach 1:
The system dynamically adjusts the operating clock frequency based on detected voltage transient conditions. When a voltage transient is detected, the clock frequency is automatically reduced to maintain timing accuracy without requiring higher voltage operation. This dynamic adaptation allows the system to maintain timing precision while avoiding the power penalty of continuous high-voltage operation.
Solution Approach 2:
The invention changes the operating parameter (clock frequency) in response to voltage transient conditions. By detecting voltage droops and adjusting the clock frequency accordingly, the system maintains timing accuracy during voltage transients without needing to operate at higher voltages, thereby reducing power dissipation while preserving timing precision.
2Adaptability or versatility
If adaptive clocking systems use DLL to generate multiple phase outputs, then clock flexibility is improved, but extraneous jitter increases
Solution Approach 1:
The system extracts and removes the harmful jitter component from the clock signal while preserving the useful phase information. By detecting the jitter introduced by the DLL and selectively filtering or compensating for it, the system maintains the adaptability benefits of multiple phase outputs while eliminating the detrimental extraneous jitter that degrades signal quality.
3Measurement precision
If clock frequency is reduced during voltage transients to maintain timing accuracy, then timing accuracy is improved, but productivity decreases
Solution Approach 1:
The system implements periodic monitoring of voltage conditions and adjusts the clock frequency in a periodic control loop. Rather than maintaining a permanently reduced clock speed, the system periodically checks for voltage transients and only reduces the clock frequency when actually needed, allowing full productivity during normal operating conditions while ensuring timing accuracy during voltage disturbances.
Data Source
AI summary
In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.