SET Suppression Circuit Using Redundant Outputs and Self-Selecting MUX
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital electronic circuits, particularly FPGAs and ASICs, are vulnerable to single event transients (SETs) which can cause temporary changes in logic values, leading to errors and crashes, especially in space-based applications, and current mitigation methods like Triple Modular Redundancy (TMR) are costly and inefficient in terms of area and power consumption.
Innovation Solution
A circuit structure using a two-input multiplexer with sub-circuits that are insensitive to changes in specific logic states, combined with a sensing circuit to disconnect affected circuits until a power reset or memory reconfiguration, effectively suppressing SETs without the need for triple modular redundancy and reducing circuit area and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Triple Modular Redundancy (TMR) is used to suppress SETs, then reliability is improved, but device complexity and area increase significantly
Solution Approach 1:
The patent introduces an intermediary SET suppression circuit that sits between the digital electronic circuit and its output. This circuit includes logic gates (AND, OR, NAND, NOR) that detect and suppress SETs by monitoring signal transitions and blocking transient errors from propagating, thereby providing reliability improvement without requiring full TMR triplication of the entire circuit.
Solution Approach 2:
The patent segments the SET suppression function into a separate, dedicated circuit module rather than replicating the entire digital electronic circuit three times. By dividing the system into the original circuit and a standalone suppression circuit with specific logic gates, the complexity overhead is dramatically reduced while maintaining reliability benefits.
2Reliability
If Triple Modular Redundancy (TMR) is used to suppress SETs, then reliability is improved, but power consumption increases
Solution Approach 1:
The intermediary suppression circuit uses power-efficient logic gates (AND, OR, NAND, NOR) that only become active when detecting signal transitions. This mediator approach consumes significantly less power than TMR which requires continuous operation of three full circuit replicas, while still providing effective SET suppression.
3Reliability
If conventional circuits are used without SET suppression, then area and power are minimized, but reliability deteriorates due to SET vulnerability
Solution Approach 1:
The patent places an intermediary suppression circuit at the output of the digital electronic circuit. This mediator monitors and filters SETs without requiring area multiplication like TMR, achieving reliability improvement with minimal area overhead by using a compact logic gate-based detection and suppression mechanism.
4Productivity
If circuit speed is increased, then productivity is improved, but sensitivity to SETs increases
Solution Approach 1:
The suppression circuit acts as a speed-independent mediator that filters SETs regardless of the operating frequency of the digital electronic circuit. By placing this intermediary between the fast-switching circuit and its output, the system can maintain high productivity while the suppression circuit continuously protects against SETs that may occur during rapid signal transitions.
Data Source
AI summary
A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100′) which receives a redundant or duplicated output of the digital electronic circuit (A′), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes. The multiplexer output (204) is provided as a final output in which SETs and glitches have been suppressed.