Setback Gate Structure for High-Voltage Oxide Integrity
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Solution Overview
Problem
High voltage transistor devices in integrated chips face reliability issues due to reduced gate oxide integrity and breakdown voltage caused by the gate layer extending over thin regions of the gate dielectric layer, leading to a reduced minimum distance between the gate layer and the substrate.
Innovation Solution
The sidewalls of the gate layer are setback from the sidewalls of the gate dielectric layer and trench isolation layer, preventing the gate layer from extending over thin regions of the gate dielectric layer, thereby increasing the minimum distance between the gate layer and the substrate, improving reliability by enhancing gate oxide integrity and breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate layer extends over the gate dielectric layer to cover the channel region, then the gate control is improved, but the gate oxide integrity deteriorates due to thin gate dielectric regions
Solution Approach 1:
The gate structure is segmented into distinct regions: a gate layer portion directly over the gate dielectric layer and sidewall spacer portions extending along the gate dielectric sidewalls. This segmentation allows the gate layer to provide control where needed while avoiding direct extension over thin dielectric regions, thus maintaining gate oxide integrity.
Solution Approach 2:
Sidewall spacers act as intermediary structures between the gate layer and the channel region. These spacers extend along the gate dielectric sidewalls and provide the necessary electrical control without requiring the gate layer to directly extend over thin gate dielectric regions, thereby preserving gate oxide integrity.
2Reliability
If the gate layer extends over thin regions of the gate dielectric layer, then the channel control is enhanced, but the breakdown voltage reduces
Solution Approach 1:
The gate structure is divided into a gate layer portion and sidewall spacer portions. The sidewall spacers extend along the gate dielectric sidewalls to provide channel control, while the gate layer remains confined to regions with sufficient dielectric thickness, thereby maintaining high breakdown voltage.
Solution Approach 2:
The gate control function is extended into the vertical dimension through sidewall spacers that extend along the gate dielectric sidewalls. This allows channel control to be achieved through vertical extension rather than horizontal extension over thin dielectric regions, preserving breakdown voltage.
3Area of stationary object
If the gate layer is positioned closer to the substrate to reduce device area, then the device footprint is reduced, but the gate oxide integrity deteriorates
Solution Approach 1:
The gate structure is segmented into a gate layer portion positioned over the gate dielectric and sidewall spacer portions extending vertically along the gate dielectric sidewalls. This segmentation enables effective channel control and acceptable device footprint without requiring the gate layer to be positioned close to the substrate over thin dielectric regions, thereby maintaining gate oxide integrity.
Data Source
AI summary
An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.