Setup Hold Time Measurement Circuit Using Internal Delay Control
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Solution Overview
Problem
Conventional methods for measuring data setup/hold time in synchronous DRAM devices require external equipment to change delay sections, leading to inefficiencies and the need for read/write operations to compare input and output data.
Innovation Solution
An apparatus that generates internal clock and data signals from an external clock signal using a test signal, allowing for the measurement of setup/hold time without read/write operations through a data generating unit, flag signal generating unit, and counter, which produce flag signals and counting signals to determine the delay section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional external equipment is used to change delay sections and compare input/output data through read/write operations, then measurement accuracy can be achieved, but measurement efficiency deteriorates
Solution Approach 1:
The patent extracts the measurement function from external equipment and implements it within the memory device itself using internal test mode circuitry. The delay section modification and setup/hold time measurement are performed internally without requiring external equipment to change delay sections or execute read/write operations, thereby improving measurement efficiency while maintaining accuracy
Solution Approach 2:
The memory device performs self-measurement of setup/hold time by utilizing its own internal resources. The test mode circuit modifies delay sections and measures timing parameters using internal signals and counters, eliminating the need for external equipment intervention and enabling efficient measurement without compromising accuracy
2Reliability
If external equipment modifies delay sections and performs read/write operations for measurement, then reliable data comparison is possible, but device complexity increases
Solution Approach 1:
The patent removes the complex external measurement equipment and its associated delay section modification mechanisms. Instead, simple internal test mode circuitry is used to modify delay sections and perform measurements, significantly reducing overall system complexity while maintaining measurement reliability through internal signal comparison
Solution Approach 2:
The measurement function is merged with the existing memory device structure. The test mode circuit integrates delay section modification, signal generation, and measurement capabilities within the memory device itself, eliminating the need for separate external equipment and reducing overall system complexity
Data Source
AI summary
An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a flag signal generating unit for generating flag signals according to the internal clock signal and the data signals, and a counter for producing the counting signals in response to the flag signals.