SEU-Immune Flip-Flop Using Vertical Resistive RC Feedback
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Solution Overview
Problem
Existing SEU immune flip-flop designs are too large due to the physical size of series resistor-capacitor (RC) networks or require excessive die area with voting circuits, making them unsuitable for compact integrated circuit implementation.
Innovation Solution
A compact SEU immune flip-flop design utilizing a vertical resistive element, such as an unprogrammed antifuse or virgin ReRAM device, in combination with gate capacitances of inverter transistors to form an RC network, providing time delay regenerative feedback for immunity against Single Event Upsets (SEUs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If series resistor-capacitor (RC) networks are used to filter out SET events, then SEU immunity is achieved, but the physical area of the flip-flop becomes too large
Solution Approach 1:
The patent changes the resistance parameter from normal sheet resistance (600-10K ohms) to extremely high resistance (100K+ ohms) achieved through unprogrammed antifuse or virgin ReRAM structures. This parameter change allows achieving the required 100K ohm resistance in a much smaller area (few squares instead of 10+ squares), resolving the contradiction between SEU immunity and area.
Solution Approach 2:
The patent uses unprogrammed antifuse or virgin ReRAM structures that are essentially non-functional (high resistance) until programmed. These structures serve as disposable high-resistance elements that can be integrated densely without occupying functional circuit area, allowing SEU immunity to be added without significant area penalty.
2Reliability
If three copies of the circuitry with voting circuit are used to provide SEU/SET immunity, then reliability is improved, but the die area consumption increases by over three times
Solution Approach 1:
The patent extracts the high-resistance filtering function from the main circuit logic and implements it separately using unprogrammed antifuse or virgin ReRAM structures. This allows the main circuit to remain compact while the SEU immunity function is provided by the extracted high-resistance elements, avoiding the need for three-fold redundancy.
Solution Approach 2:
The unprogrammed antifuse or virgin ReRAM structure acts as an intermediary element between the circuit nodes, providing the high-resistance filtering effect without requiring duplicate circuitry. This intermediary structure enables SEU immunity with minimal area overhead compared to the three-copy voting approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves SEU immunity with a significantly reduced footprint, allowing for smaller integrated circuit implementation while maintaining effective protection against SEUs, thus enabling stable operation in mission-critical applications.
Implementation Method 1
a vertical resistive element, such as an unprogrammed antifuse or virgin ReRAM device, in combination with gate capacitances of inverter transistors to form an RC network, providing time delay regenerative feedback
Data Source
AI summary
An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.