SEU-Hardened SRAM Cell Using Resistor Feedback
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Solution Overview
Problem
Conventional static random access memory (SRAM) cells are susceptible to single event upsets (SEUs) in high-radiation environments, such as satellite orbital space, due to energetic particles generating critical charges that can alter the logic state of memory cells.
Innovation Solution
The implementation of SEU-hardened memory cells with specific resistor and capacitor configurations, including cross-coupled inverters, resistors connected between transistors, and capacitors to provide positive feedback and maintain the original logic state during SEU events, reducing the impact of energetic particles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional six-transistor memory cells are used, then device complexity is reduced and ease of manufacture is improved, but reliability deteriorates in high-radiation environments due to susceptibility to single event upsets
Solution Approach 1:
The patent applies preliminary action by pre-charging storage nodes to specific voltage levels (e.g., 0.7V for logic 0, 1.8V for logic 1) before radiation exposure. This pre-establishment of voltage margins creates a buffer that resists SEU-induced charge changes, allowing the cell to maintain its logic state despite particle strikes.
Solution Approach 2:
The patent changes critical parameters including storage node voltage levels (0.7V/1.8V), transistor threshold voltages (0.35V/0.45V), and resistor values (500kΩ/1MΩ) to optimize SEU hardness. By carefully selecting these parameters, the cell achieves enhanced radiation tolerance while maintaining functionality.
2Reliability
If resistor and capacitor configurations are added to harden against SEUs, then reliability improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The resistors and capacitors in the patent serve multiple functions: they provide positive feedback for logic state reinforcement, act as charge storage elements, and establish voltage division ratios that determine threshold levels. This multi-functionality reduces the need for additional dedicated components, simplifying manufacturing.
Solution Approach 2:
The patent implements positive feedback through resistor networks that reinforce the dominant logic state. When one storage node experiences a voltage change due to SEU, the feedback mechanism amplifies the opposing node's state, ensuring rapid recovery to the original logic configuration and maintaining data integrity.
3Reliability
If positive feedback mechanisms are implemented to maintain logic state, then reliability against SEUs improves, but energy consumption increases
Solution Approach 1:
The patent employs periodic refresh operations where the memory cell state is periodically reinforced through the positive feedback mechanism. Rather than continuous energy consumption, the feedback activates periodically to maintain logic states, reducing overall power usage while ensuring stability during SEU events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively hardens SRAM cells against SEUs, ensuring data integrity in high-radiation environments by reinforcing the original logic state during transient events and allowing for reliable data storage in SRAMs.
Implementation Method 1
a capacitor connected between a first node and a second node
Implementation Method 2
a first resistor connected between a source of a first transistor and a drain of a second transistor within the first inverter
Data Source
AI summary
A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.