SEU-Hardened Memory Array Layout Against Multiple-Cell Upsets
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Solution Overview
Problem
Current CMOS memory arrays are vulnerable to multiple-cell upsets from high-energy particle hits, which can render the memory array useless until true values are restored, especially as design technology decreases and redundant nodes become closer together.
Innovation Solution
A memory array with a four-plex of SEU-hardened memory cells, each oriented differently and having a distinct critical ion track, reducing the probability of a single ion upsetting adjacent cells by ensuring each cell has a unique orientation and ion track, thereby minimizing simultaneous upsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are arranged in conventional arrays, then manufacturing and operation are simple, but the array is vulnerable to multiple-cell upsets from high-energy particle hits
Solution Approach 1:
The memory array is segmented into multiple banks (first bank, second bank, third bank, fourth bank) with different orientations. Each bank contains memory cells arranged in specific patterns (e.g., rows oriented in first direction, columns in second direction; or vice versa). This segmentation ensures that a single ion track cannot affect all banks simultaneously, reducing multiple-cell upsets while maintaining overall array functionality.
Solution Approach 2:
Different banks are configured with asymmetric orientations relative to each other. For example, the first bank has rows in the first direction and columns in the second direction, while the second bank has rows in the second direction and columns in the first direction. This asymmetric arrangement ensures that critical ion tracks affecting one bank do not align with critical tracks in other banks, thereby preventing simultaneous upsets across multiple banks.
2Volume of moving object
If design technology decreases, then device size reduces, but redundant nodes become closer together increasing vulnerability to ion hits
Solution Approach 1:
The patent introduces a spatial dimension solution by orienting different banks in different directions. Instead of increasing separation distance within a single orientation (which would increase area), the solution uses multi-directional arrangement to create geometric separation. Ion tracks are primarily linear and directional, so by orienting banks perpendicular to each other, the patent ensures that ion tracks affecting one bank are unlikely to affect adjacent banks, effectively using dimensional orientation to combat the harmful effect of reduced node separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the likelihood of multiple-cell upsets, enhancing the radiation tolerance of memory arrays and maintaining data integrity even under ultra-high-energy particle exposure.
Implementation Method 1
An ion hit creates charge in the silicon of the memory cell. This charge can upset the data value stored at a node by changing the voltage at that node.
Data Source
AI summary
An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells has a different critical ion track. Providing a four-plex of SEU-hardened memory cells, each with a different critical ion track, reduces the probability of a single ion upsetting adjacent memory cells.