Serial Bit Stream Alignment by SFD Bit Shift Correction
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Solution Overview
Problem
Serializer/deserializer systems face issues with bit shifting and corruption during bit locking, leading to frame loss due to misalignment of the transmit data clock and embedded serial data clock, especially when the first bit of the preamble is received out of phase.
Innovation Solution
A method and circuit that latch Q bits from the serial bit stream into a register, locate the position of the first bit of the Start of Frame Delimiter (SFD), and discard P-1 bits from the serial bit stream to align it with the parallel output, utilizing fault-tolerant analysis logic to correct for bit shifts and corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transmit data clock is used to serialize data, then data transmission is achieved, but the clock may not be in phase with the embedded serial data clock, causing bit shifting and frame loss
Solution Approach 1:
The patent applies preliminary action by inserting a preamble with a known special pattern before the actual data frame. This preamble allows the receiver to perform bit locking and phase alignment before the main data arrives, preventing bit shifting during data transmission. The DPLL uses the preamble pattern to acquire lock and synchronize the transmit data clock with the embedded serial data clock in advance.
Solution Approach 2:
The patent implements feedback through a Digital Phase Lock Loop (DPLL) that continuously monitors the phase difference between the transmit data clock and the recovered serial data clock. The DPLL adjusts the clock phase based on feedback from the preamble pattern recognition, ensuring sustained synchronization throughout data transmission and preventing bit alignment errors.
2Reliability
If the DPLL synchronizes clocks during the preamble, then clock alignment is achieved, but the DPLL may miss or gain bits, causing bit corruption
Solution Approach 1:
The patent uses the preamble as a preliminary synchronization sequence with a known special pattern. The DPLL acquires lock and determines the correct bit count during this preamble phase before actual data transmission begins. This preliminary bit counting during the preamble ensures that the receiver knows exactly how many bits to expect in the frame, preventing bit gain or loss during data reception.
Solution Approach 2:
The patent changes the parameter being measured from continuous phase adjustment to discrete bit counting based on the known preamble pattern. By using the special pattern in the preamble as a reference, the system determines the exact bit position and count, transforming the synchronization problem from a continuous phase alignment issue to a discrete counting problem that can be accurately resolved.
3Reliability
If bit locking is performed using the preamble, then clock recovery is achieved, but bit shifting may occur causing the preamble to be unrecognized and the frame to be lost
Solution Approach 1:
The patent performs bit locking and clock recovery during the preamble phase before actual data transmission. The receiver uses the known special pattern in the preamble to establish accurate bit alignment and clock synchronization in advance. This preliminary bit locking ensures that when the main frame arrives, the receiver is already properly synchronized and can accurately recognize and process the data without frame loss.
Solution Approach 2:
The patent uses a known copy or template of the special preamble pattern as a reference for comparison. The receiver has a stored copy of the expected preamble pattern and compares the received bits against this template during the bit locking process. This pattern matching approach enables accurate recognition of the preamble even in the presence of minor disturbances, ensuring reliable frame detection.
Data Source
AI summary
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.