SFI 4.2 Asynchronous Channel Transport Using 66/64-Bit Interleaving
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Solution Overview
Problem
The existing SFI4.2 interface is synchronous and incapable of supporting asynchronous signals or combinations of asynchronous sub-rate signals, requiring increased operating rates to transport asynchronous data channels, which is inefficient.
Innovation Solution
A SerDes Frame Interface (SFI) 4.2 system that handles 10 G signals, four asynchronous 2.5 G signals, or combinations of 1.25 G and 2.5 G signals by interleaving 8-bit data bytes with a unique clock and using 'data valid' signaling to transport them synchronously across the interface, adding a 2-bit control word to create 66/64-bit data blocks for transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the SFI4.2 interface is designed as a synchronous interface with one clock and four data lines, then the interface achieves simplicity and synchronous operation, but it cannot support asynchronous signals or combinations of asynchronous sub-rate signals
Solution Approach 1:
The interface is segmented into multiple independent data lanes (four 2.5 G lanes) that can operate asynchronously. Each lane is treated as an independent channel that can carry data at different rates, allowing the interface to support both synchronous and asynchronous operations without requiring a complete redesign of the interface structure.
Solution Approach 2:
The SFI4.2 interface is designed to be universal by enabling it to handle multiple signal types (synchronous 10 G, asynchronous 2.5 G, asynchronous 1.25 G) through the same physical infrastructure. The interface can dynamically adapt to different signal combinations, making it multi-functional without requiring separate dedicated interfaces for each signal type.
2Adaptability or versatility
If asynchronous sub-rate signals are mapped to another frequency to transport across SFI4.2, then the interface can transmit asynchronous data channels, but the operating rate of the SFI4.2 interface increases to higher than required
Solution Approach 1:
The interface dynamically changes its operational parameters based on the input signal characteristics. When asynchronous sub-rate signals are detected, the interface adjusts its timing and synchronization parameters to accommodate the lower data rates without forcing all lanes to operate at the maximum 10 G rate. This allows efficient transmission at variable speeds matching the actual data requirements.
3Adaptability or versatility
If the interface transmits data at a fixed line clock rate, then the transmission is simple and synchronized, but it cannot accommodate multiple asynchronous clock rates
Solution Approach 1:
The clock synchronization mechanism is made dynamic rather than static. The interface can adapt its clocking behavior based on the input signals, allowing different lanes to operate at different clock rates when needed. This dynamic approach enables the interface to handle multiple asynchronous clock rates while maintaining operational simplicity through automated adaptation.
4Productivity
If data is transmitted without validity signaling, then the transmission overhead is reduced, but there is no way to indicate data validity for asynchronous channels
Solution Approach 1:
Validity signaling is extracted as a separate control function from the main data transmission path. By using dedicated control bits within the existing data structure rather than adding separate signaling channels, the interface can indicate data validity for asynchronous channels while minimizing the impact on transmission efficiency. This extraction approach allows validity information to be carried within the existing protocol framework.
Data Source
AI summary
A system and method are provided for transmitting and receiving asynchronous channels of information via a SerDes Frame Interface (SFI) 4.2 interface. The SerDes device accepts a plurality of channels operating at asynchronous channel clock rates. Bytes of data from each channel are loaded into a source at the channel clock rates. Once loaded, the bytes of data for each channel are drained from the source at a line clock rate and interleaved into four 64-bit segments. A 2-bit control word is added to each segment, creating 66/64-bit data blocks. The control word indicates the validity of bytes of data within the 66/64-bit data blocks. Then, the 66/64 bit data blocks are transmitted via a SFI4.2 interface in four lanes, at a rate proportional to the line clock rate.