SoC Special Function Register Clock Gating for Power Reduction
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Solution Overview
Problem
Current system-on-chip (SoC) designs face challenges in minimizing power consumption, particularly in managing clock supply to special function registers (SFRs) based on operating modes and update attributes, leading to inefficient power management.
Innovation Solution
The proposed SoC incorporates a special function register with first and second update storage elements and corresponding update logics, enabling clock gating to minimize power consumption by selectively supplying clocks based on the operating mode and update attributes, with distinct clocks for different storage elements and statuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clocks are continuously supplied to all storage elements in SFR, then the SFR can maintain readiness for any operation, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating where clocks are supplied to storage elements based on their update attributes and current operating mode. The update logics dynamically enable or disable clock supply to specific storage elements (first update storage element or second update storage element) according to whether they require bus updates, toggle updates, or shadow register updates, thereby reducing power consumption while maintaining operational readiness when needed
Solution Approach 2:
The SFR is segmented into multiple storage elements with different update attributes (bus update, toggle update, shadow register update), each with its own update logic. This segmentation allows independent clock gating control for each storage element based on its specific update requirements, rather than supplying clocks to all elements uniformly, thus reducing overall power consumption while maintaining necessary functionality
2Productivity
If multiple storage elements are updated simultaneously, then the SFR can respond to multiple operations, but clock management complexity increases
Solution Approach 1:
Each storage element is assigned a specific update attribute (bus update, toggle update, or shadow register update) with corresponding local update logic. The clock gating is applied locally to each storage element based on its update attribute rather than using a unified clock management approach, allowing simultaneous updates of different storage elements while keeping individual clock management simple and attribute-specific
Data Source
AI summary
Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.