SGD Bias Control for Pre-read Cycle Timing Shrink
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Solution Overview
Problem
As the number of wordlines increases in memory devices, the time required for read operations also increases due to longer R2 clock timing, leading to performance inefficiencies and potential injection type disturb during channel discharge.
Innovation Solution
Implementing unselected SGD ramp down control, R2 timing control by page, and R2 timing control by wordline, including specific voltage ramping strategies during pre-read cycles to optimize read operation timing and reduce R2 clock duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of wordlines is increased to improve memory capacity, then the storage capacity is improved, but the read operation time increases due to longer R2 clock timing
Solution Approach 1:
The patent applies dynamics by making the R2 clock timing adjustable rather than fixed. The control circuit dynamically adjusts the R2 clock timing based on the specific wordline being read, allowing optimization of read operation time for each wordline while maintaining high memory capacity through increased wordline count
Solution Approach 2:
The patent changes the parameter of R2 clock timing from a fixed value to a variable parameter that can be adjusted per wordline. This allows the system to maintain long R2 timing for capacity while reducing it for specific read operations to improve speed
2Reliability
If the R2 clock timing is extended to ensure complete channel discharge, then the reliability is improved, but the injection type disturb increases during channel discharge
Solution Approach 1:
The patent applies local quality by treating different wordlines differently in terms of R2 timing. Instead of a uniform approach, each wordline receives optimized timing parameters based on its specific characteristics and position, reducing injection disturb in less critical areas while maintaining reliability where needed
Solution Approach 2:
The dynamic adjustment of R2 timing allows the system to extend timing only when necessary for reliability while reducing it during periods when injection disturb is more likely, creating a flexible solution that balances both requirements
3Productivity
If the read operation timing is optimized for speed, then the productivity is improved, but the risk of incomplete channel discharge increases
Solution Approach 1:
The system dynamically adjusts R2 timing based on real-time conditions and wordline characteristics, allowing faster read operations when channel discharge is certain to be complete while extending timing when completeness is at risk, thus optimizing both speed and reliability
Data Source
AI summary
A method of operating a non-volatile semiconductor memory device is disclosed. The method comprises: during a first pre-read cycle of a read operation, ramping up a control signal on a wordline selected for the read operation to a first target pre-read voltage and ramping up a control signal on a drain-side select (SGD) transistor of an unselected string of the plurality of strings to a second target pre-read voltage. The method further comprises during a second pre-read cycle of the read operation, ramping down the control signal on the wordline to a target read voltage and ramping down the control signal on the SGD transistor of the unselected string to a third target pre-read voltage after a delay period after the triggering edge of the second pre-read cycle.