SGD Transistor Disturb Suppression in 3D NAND Erase
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Solution Overview
Problem
In 3D NAND memory devices, there is a challenge in avoiding disturbs of select gate transistors during the erase operation, particularly due to channel gradients that can occur when the control gate voltage of the SGD transistor is floated before the channel is sufficiently charged, leading to unintended erasure of these transistors.
Innovation Solution
A voltage detector connected to the bit line monitors the channel charging and floats the control gate voltage of the SGD transistor only when the bit line voltage reaches a reference voltage, ensuring the channel is adequately charged to prevent disturbs, and the erase voltage is ramped in steps to minimize coupling to the control gate, reducing the risk of disturb during the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the control gate voltage of the SGD transistor is floated early during erase operation, then the erase speed is improved, but the select gate transistor may be inadvertently erased (disturb)
Solution Approach 1:
The control gate voltage of the SGD transistor is floated only after the channel voltage has reached a threshold level, ensuring that the channel is sufficiently charged before the transistor is left in a high-impedance state. This preliminary charging action prevents inadvertent erasure of the select gate transistor while still enabling fast erase operation.
Solution Approach 2:
The system monitors the channel voltage level and uses this feedback to determine when to float the control gate voltage of the SGD transistor. This feedback mechanism ensures that the channel is adequately charged before transitioning to the floating state, preventing disturb while optimizing erase speed.
2Loss of time
If the substrate voltage is rapidly increased to the final level, then the erase operation is completed faster, but channel gradient causes disturb to the SGD transistor
Solution Approach 1:
The substrate voltage increase is divided into multiple stages: first increasing to an intermediate level, waiting for channel charging, then increasing to the final level. This segmentation of the voltage ramping process eliminates harmful channel gradients while maintaining efficient erase operation.
Solution Approach 2:
The erase operation uses periodic voltage ramping with intermediate holding phases. The substrate voltage is increased, held at an intermediate level to allow channel charging, then increased further. This periodic action pattern prevents disturb while completing the erase operation efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the disturbs of SGD transistors by ensuring the channel is fully charged before floating the control gate voltage, maintaining the integrity of the memory cells and improving the reliability of the erase operation in 3D NAND memory devices.
Implementation Method 1
the voltages of non-user data storage elements are capacitively coupled higher by controlled increase in an erase voltage which is applied to a substrate
Implementation Method 2
A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage
Data Source
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AI summary
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the string. However, there is a delay in charging up a drain end of the channel. A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage. When the reference voltage is reached, a voltage of the select gate transistor at the drain end of the string can be floated. This avoids unintentional programming of the select gate transistor which could otherwise occur if the voltage was floated to soon. Also, a substrate voltage may be ramped up to a first detected level before being ramped up to a second, final level.