Surround Gate Transistor Concave Source Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor device with a surrounding gate transistor (SGT) experiences increased power consumption due to high off-leak current, which is exacerbated by the miniaturization of ultra-large-scale integrated circuits, leading to challenges in reducing the off-leak current effectively.
Innovation Solution
The semiconductor device incorporates a design where the source and drain regions are formed in a concave shape, with specific impurity regions and high-concentration impurity regions strategically positioned to enhance the punch-through voltage and reduce off-leak current, utilizing ion implantation at oblique angles to form concave diffusion layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length is reduced for miniaturization, then the occupancy area is reduced, but the off-leak current increases
Solution Approach 1:
The source and drain regions are formed with concave curved surfaces instead of flat surfaces. This curvature increases the punch-through voltage by creating a potential barrier that prevents carrier flow when the transistor is off, thereby reducing off-leak current while maintaining small gate length and occupancy area.
Solution Approach 2:
The concavity depth parameter is optimized to achieve the desired punch-through voltage. By controlling the depth of the concave structure in the source and drain regions, the potential barrier height is adjusted to suppress off-leak current while maintaining compatibility with miniaturized gate lengths.
2Object-generated harmful factors
If the source and drain are formed in a concave structure to increase punch-through voltage, then the off-leak current is reduced, but the manufacturing complexity increases
Solution Approach 1:
The concave structure is formed by extending the source and drain regions in the vertical dimension rather than increasing lateral dimensions. This vertical extension creates the desired curvature and potential barrier without significantly increasing the lateral footprint or overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces off-leak current and increases punch-through voltage, allowing for more efficient operation with smaller gate lengths and reduced power consumption, while maintaining low sub-threshold swing characteristics.
Implementation Method 1
utilizing ion implantation at oblique angles to form concave diffusion layers
Data Source
AI summary
A semiconductor device includes a first-conductive type first pillar, a first dielectric surrounding the first pillar, a gate surrounding the dielectric, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface with the first pillar, and a first-conductive type region surrounded by the second-conductive type region. The third pillar has a second-conductive type impurity region in a surface thereof except a part of a contact surface with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region of the third pillar. The first-conductive type region of each of the second and third pillars has a length greater than that of a depletion layer extending from a base of the second-conductive type region of one of the second and third pillars.