Surrounding Gate Transistor Dummy Gate Process
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Solution Overview
Problem
The challenge in producing Surrounding Gate Transistors (SGTs) lies in the difficulty of suppressing leak current in nanoscale MOS transistors, which hinders the reduction of circuit area, and existing production methods require multiple masks and a metal-gate last process, leading to inefficiencies and misalignment issues.
Innovation Solution
A method employing a gate last process using two masks to form a fin-shaped and pillar-shaped semiconductor layer, a gate electrode, and a gate line, with the formation of dummy gates and hard masks to facilitate the deposition of metal and reduce the number of steps, preventing partial filling of holes and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal-gate last process is employed to successfully perform metal-gate process and high-temperature process, then the reliability of the transistor is improved, but the device complexity and number of manufacturing steps increase
Solution Approach 1:
The patent forms dummy gates and hard masks in advance before the metal deposition step. The dummy gates are created using polysilicon and nitride films, and the hard masks are prepared on the side walls of the dummy gates. This preliminary preparation enables the subsequent metal-gate last process to proceed smoothly without requiring additional alignment steps, thus maintaining reliability while reducing process complexity
Solution Approach 2:
The patent introduces dummy gates as intermediary structures that facilitate the metal-gate last process. These dummy gates serve as placeholders and reference structures during the manufacturing process, enabling precise metal deposition and subsequent removal of the dummy gates. This intermediary approach simplifies the overall process by providing clear alignment references without adding permanent structural complexity
2Manufacturing precision
If three masks are used to form the silicon pillar, planar silicon layer, and gate line, then the manufacturing precision is improved, but the device complexity and production time increase
Solution Approach 1:
The patent combines the formation of multiple structures into a single etching step. By using a unified mask pattern that defines both the silicon pillar and the planar silicon layer simultaneously, the process reduces the number of separate masking steps from three to two. This merging approach maintains manufacturing precision through self-alignment while reducing device complexity and production time
Solution Approach 2:
The patent creates mask structures that serve multiple functions. The same mask pattern is used to define both the silicon pillar and the planar silicon layer, making the mask universally applicable for multiple structural definitions. This multi-functional mask approach reduces the total number of masks required while maintaining the precision needed for each individual structure
3Ease of manufacture
If metal is deposited to fill a hole with upper portion narrower than lower portion, then the ease of manufacture is improved, but the manufacturing precision deteriorates due to partial filling
Solution Approach 1:
The patent forms dummy gates and hard masks before metal deposition to create a structured template. The dummy gates provide a defined geometry that guides metal deposition, ensuring complete and uniform filling. The hard masks on the side walls prevent metal from adhering to unwanted surfaces. This preliminary structuring enables easy metal deposition while maintaining precision by preventing partial filling
Solution Approach 2:
The dummy gates act as intermediary structures that mediate the metal deposition process. They provide a controlled geometry that ensures complete metal filling while preventing metal from spreading to adjacent regions. After metal deposition, the dummy gates are removed, leaving precisely formed metal gates. This intermediary approach simplifies manufacturing while maintaining high precision
4Area of stationary object
If the size of MOS transistors is reduced to nanometer order to increase integration density, then the area is reduced, but the reliability deteriorates due to increased leak current
Solution Approach 1:
The patent transitions from planar transistor geometry to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area and gate control without increasing the planar footprint. The vertical structure provides better electrostatic control over the channel, suppressing leak current while maintaining small device area and high integration density
Solution Approach 2:
The patent implements a surrounding gate structure where the gate electrode wraps around the fin structure in three dimensions. This nested configuration provides maximum gate control over the channel from multiple directions, effectively suppressing leak current in nanoscale devices. The gate is positioned both above and below the fin, creating a nested arrangement that enhances control without increasing lateral dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient formation of SGTs with reduced parasitic capacitance and improved insulation, enabling effective metal-gate formation and minimizing the number of steps required, thus enhancing the integration density and reducing leak current issues.
Implementation Method 1
forming a gate insulating film around the pillar-shaped semiconductor layer
Implementation Method 2
depositing metal around the gate insulating film to form a gate electrode
Data Source
AI summary
An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.