Self-Aligned SGT Fabrication via Gate-Last Process
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Solution Overview
Problem
The increasing integration and miniaturization of semiconductor integrated circuits, particularly MOS transistors, face challenges in suppressing leak currents and forming nano-scale MOS transistors due to the difficulty in reducing the area occupied by circuits while maintaining necessary currents, which is exacerbated by the complexity of forming pillar-shaped semiconductor layers and deep contact holes in surrounding gate transistors.
Innovation Solution
A method for producing a semiconductor device that employs a gate-last process, where a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line are formed by self-alignment, using a dummy gate and dummy contact, and a metal gate-last process is used to simplify the formation of a metal gate SGT structure, reducing the number of steps and eliminating the need for deep contact hole formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three masks are used to form silicon pillar, planar silicon layer, and gate line separately, then each component can be formed with precise control, but the manufacturing process becomes complex and the number of steps increases
Solution Approach 1:
The patent combines the formation of the silicon pillar, planar silicon layer, and gate line into a single etching step using one mask pattern. The mask is designed with specific pattern rules that allow all three components to be formed simultaneously through self-alignment, eliminating the need for three separate masking steps and reducing process complexity while maintaining precision.
Solution Approach 2:
The patent performs preliminary actions by forming the mask with pre-calculated pattern dimensions and orientations that account for subsequent self-aligned etching. The mask pattern is designed in advance to automatically generate the correct geometries of silicon pillars, planar silicon layers, and gate lines without requiring additional alignment steps, thus simplifying the manufacturing process.
2Reliability
If deep contact holes are formed to connect upper portion of planar silicon layer and metal wire, then electrical connection is achieved, but etching rate decreases and resist is etched away due to high aspect ratio
Solution Approach 1:
The patent extracts the need for deep contact holes by redesigning the electrical connection path. Instead of forming deep vertical contact holes through the planar silicon layer, the invention uses the self-aligned structure where the gate line and contact structures are formed in the same etching step, eliminating the requirement for separate deep contact hole formation and associated high aspect ratio etching challenges.
Solution Approach 2:
The patent transitions from vertical deep contact hole formation to a planar self-aligned structure where connections are established through the lateral arrangement of components formed in a single etching step. This dimensional shift from vertical to lateral connectivity avoids the high aspect ratio problem entirely.
3Adaptability or versatility
If metal gate-last process is employed to achieve both metal gate and high-temperature process, then compatibility is improved, but the number of process steps increases
Solution Approach 1:
The patent merges the formation of multiple structural components (silicon pillar, planar silicon layer, gate line) into a single self-aligned etching step. This consolidation reduces the overall number of process steps required in the metal gate-last process, making the methodology more efficient while maintaining compatibility with high-temperature processing requirements.
4Object-affected harmful factors
If first insulating film is formed around fin-shaped semiconductor layer to decrease parasitic capacitance, then parasitic capacitance is reduced, but the structure becomes more complex when pillar-shaped semiconductor layer is also present
Solution Approach 1:
The patent applies a universal insulating film formation process that simultaneously handles both fin-shaped and pillar-shaped semiconductor structures. The self-aligned etching methodology ensures that the insulating film is deposited and patterned in a way that uniformly addresses parasitic capacitance reduction for both structure types without requiring separate processing steps, thus reducing overall device complexity.
Data Source
AI summary
A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.