SGT Memory Device Capacitive Coupling Noise Reduction
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Solution Overview
Problem
In capacitor-less single-transistor DRAM memory devices, strong capacitive coupling between the word line and the floating-state SGT body leads to noise transmission during read/write operations, causing erroneous data storage and making it difficult to implement these devices practically, while also requiring high-density and low-cost peripheral circuit formation on the memory cell substrate.
Innovation Solution
The memory device incorporates a specific structure with multiple gate conductor layers and insulating layers to control voltages and perform memory operations, including a first semiconductor base with impurity layers and gate insulating layers, and gate conductor layers that surround the semiconductor base to reduce capacitive coupling and enhance operational margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strong capacitive coupling between word line and floating-state SGT body is used for memory operation, then memory write/read operations can be performed, but noise is transmitted to the SGT body causing erroneous data storage
Solution Approach 1:
A plate line is introduced as an intermediary between the word line and the SGT body. The plate line acts as a shield that blocks the capacitive coupling noise from reaching the SGT body during memory operations, while still allowing the necessary electric field control for write and read operations to function properly.
2Device complexity
If capacitor-less single-transistor DRAM structure is used to increase integration density, then device complexity is reduced, but operational margin between '1' and '0' states becomes insufficient
Solution Approach 1:
The gate structure is segmented into multiple components: the word line for control, the plate line for noise shielding, and the floating body as the storage node. This segmentation allows independent optimization of each component's function, enabling noise reduction while maintaining the simple single-transistor structure for high integration density.
3Ease of manufacture
If simple single-transistor structure is used for capacitor-less DRAM, then manufacturing cost and device complexity are reduced, but noise during read/write operations increases
Solution Approach 1:
The plate line functionality is merged with the existing gate structure of the single transistor. The plate line is formed as an additional conductive layer that shares the same physical space and fabrication process as the gate, combining noise shielding functionality with the simple single-transistor structure without requiring separate complex circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces capacitive coupling noise, increases the operational margin between '1' and '0' states, and allows for stable memory operations, enabling the practical use of capacitor-less single-transistor DRAM devices with improved performance and integration density.
Implementation Method 1
a first gate conductor layer and a second gate conductor layer which are isolated from each other and surround a first gate insulating layer, the first gate conductor layer and the second gate conductor layer being disposed such that an electron group and a hole group generated due to an impact ionization phenomenon or a gate induced drain leakage current are held in a first semiconductor base
Implementation Method 2
a first gate conductor layer and a second gate conductor layer which are isolated from each other and surround a first gate insulating layer, the first gate conductor layer and the second gate conductor layer being disposed such that an electron group and a hole group generated due to an impact ionization phenomenon or a gate induced drain leakage current are held in a first semiconductor base
Implementation Method 3
a third gate conductor layer surrounding a second gate insulating layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer being disposed such that voltages applied to a first impurity layer, a second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are controlled to perform a memory write operation, a memory read operation, and a memory erase operation
Data Source
AI summary
An N+ layer connects to the bottom portion of a Si pillar standing on a substrate 1 and an N+ layer connects to the top portion of the Si pillar. Of the N+ layer and the N+ layer, one serves as the source and the other serves as the drain. A region of the Si pillar between the N+ layer and the N+ layer serves as a channel region. A first gate insulating layer surrounds the lower portion of the Si pillar and a second gate insulating layer surrounds the upper portion of the Si pillar. The first gate insulating layer and the second gate insulating layer are respectively disposed in contact with or near the N+ layers serving as the source and the drain. A first gate conductor layer and a second gate conductor layer surround the first gate insulating layer. The first gate conductor layer and the second gate conductor layer are formed so as to surround the first gate insulating layer and to be isolated from each other. A third gate conductor layer surrounds the second gate insulating layer. Thus, a dynamic flash memory cell is formed.