Surrounding Gate Transistor Fabrication via Self-Aligned Metal Gate
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Solution Overview
Problem
The increasing integration and miniaturization of semiconductor devices, particularly MOS transistors, face challenges in suppressing leak currents and forming deep contact holes due to the high aspect ratio of contact holes and thin resist layers, which complicates the production of surrounding gate transistors (SGTs) and requires multiple masks and processes.
Innovation Solution
A method for producing SGTs using a gate-last process that involves self-alignment to form fin-shaped and pillar-shaped semiconductor layers, gate electrodes, and gate lines, with dummy gates and contacts, reducing the number of steps and eliminating the need for deep contact hole formation by employing reverse-taper etching and atomic layer deposition for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of MOS transistors is decreased to nano-scale dimensions to increase integration, then the degree of integration is improved, but leak currents increase and area reduction becomes difficult
Solution Approach 1:
The patent transitions from planar MOS transistors to three-dimensional surrounding gate transistors (SGTs) with vertically arranged source, gate, and drain. This dimensional change enables better electrostatic control and leak current suppression while maintaining small footprint, resolving the contradiction between integration density and reliability.
Solution Approach 2:
The gate electrode is designed to surround the pillar-shaped semiconductor layer in a nested configuration, with the gate wrapping around the channel region. This nested structure provides enhanced control over the channel and effective suppression of leak currents while occupying minimal area.
2Manufacturing precision
If three masks are used to form silicon pillar, planar silicon layer, and gate line in typical SGT production, then the structure is formed correctly, but the manufacturing process becomes complex
Solution Approach 1:
The patent combines the formation of the gate electrode and gate line into a single metal deposition step performed after polysilicon removal. This merging of previously separate masking steps reduces process complexity while maintaining the required structural precision through self-alignment mechanisms.
Solution Approach 2:
The patent performs preliminary formation of polysilicon gates and insulating films before final metal gate deposition. This preliminary action allows subsequent self-aligned removal of polysilicon to define the gate electrode position, simplifying the final metal patterning step and reducing the number of required masks.
3Reliability
If deep contact holes are formed to connect upper portion of planar silicon layer and metal wire, then electrical connection is achieved, but etching rate decreases due to high aspect ratio
Solution Approach 1:
Instead of forming deep contact holes through the entire thickness, the patent inverts the approach by forming shallow contact holes only through the interlayer insulating film to reach the metal wire, eliminating the need for deep etching while maintaining electrical connection reliability.
4Length of moving object
If resist thickness is decreased with pattern size reduction, then miniaturization is achieved, but resist is etched during etching making deep contact hole formation difficult
Solution Approach 1:
The patent extracts the problematic deep contact hole formation step entirely from the process. By eliminating the need for deep etching through structural redesign, the issue of thin resist being etched away during deep hole formation is completely avoided, allowing continued miniaturization without compromising resist integrity.
5Adaptability or versatility
If metal gate is formed after high-temperature process in metal gate-last process, then both metal gate process and high-temperature process are achieved, but the process sequence becomes complex
Solution Approach 1:
The patent performs preliminary formation of all insulating films and polysilicon structures before the final high-temperature metal gate deposition. This preliminary action allows subsequent removal of polysilicon gates to define metal gate regions, enabling the metal gate-last process to be implemented with reduced sequence complexity.
Solution Approach 2:
The patent merges the gate electrode and gate line formation into a single metal deposition step performed after polysilicon removal. This combining of previously separate steps simplifies the process sequence while maintaining compatibility between metal gate and high-temperature processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the production process, reduces the risk of hole formation during metal filling, and effectively insulates gate electrodes and lines, enabling efficient semiconductor device fabrication with improved current retention and reduced parasitic capacitance.
Implementation Method 1
employing reverse-taper etching and atomic layer deposition for insulation
Data Source
AI summary
A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.