Surrounding Gate Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
The challenge in semiconductor technology is to reduce parasitic capacitance between a gate line and a substrate while efficiently manufacturing CMOS Surrounding Gate Transistors (SGTs) using a gate last process, particularly in forming nMOS and pMOS SGTs from a single dummy pattern, which is complicated by the need to manage metal gate contamination and high-temperature processes.
Innovation Solution
A semiconductor device structure and manufacturing method involving fin-shaped and pillar-shaped silicon layers with specific diffusion layers and insulating films, allowing for the formation of nMOS and pMOS SGTs from a single dummy pattern using a gate last process, reducing parasitic capacitance and enabling high integration by forming a metal gate electrode after polysilicon gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate is formed before high-temperature processes, then the gate electrode resistance is decreased and depletion is suppressed, but metal contamination occurs during subsequent high-temperature processes
Solution Approach 1:
The patent applies preliminary action by forming the metal gate electrode before the high-temperature processes, but protects it from contamination through a cap structure. The cap layer is deposited over the metal gate before high-temperature processing, preventing metal contamination while allowing the metal gate to provide its low-resistance benefits. After processing, the cap is removed to reveal the clean metal gate.
2Object-affected harmful factors
If a metal gate last process is used to avoid metal contamination, then high-temperature processes can be performed without contamination, but the gate electrode resistance cannot be optimized and depletion cannot be suppressed
Solution Approach 1:
The patent performs the metal gate formation in advance before high-temperature processes, rather than using a metal gate last process. This preliminary action allows the metal gate to be formed with optimal properties while protecting it from subsequent contamination through the cap structure, eliminating the need to wait until after high-temperature processing.
Solution Approach 2:
The patent introduces a cap layer as an intermediary protective structure between the metal gate and the high-temperature processing environment. This cap layer acts as a barrier that prevents metal contamination during high-temperature processes while allowing the metal gate to maintain its low-resistance properties. The cap is temporarily present during processing and then removed.
3Productivity
If fins are formed using conventional methods, then transistor structures are created, but parasitic capacitance between gate line and substrate increases
Solution Approach 1:
The patent transitions from conventional planar fin structures to three-dimensional surrounding gate transistor structures. By forming pillars that extend vertically from the substrate and surrounding them with gates in multiple dimensions, the design reduces the parasitic capacitance between the gate line and substrate. The surrounding gate configuration allows the gate to wrap around the pillar, increasing effective gate control while reducing parasitic effects.
Solution Approach 2:
The patent segments the transistor structure into distinct components: pillars formed from the substrate, insulating films surrounding the pillars, and gates wrapped around the pillars. This segmentation allows each component to be optimized independently, with the insulating film specifically addressing parasitic capacitance reduction while the pillar structure maintains efficient transistor formation.
4Manufacturing precision
If nMOS and pMOS transistors are formed separately, then each transistor type can be optimized, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The patent merges the formation processes for nMOS and pMOS transistors into a unified surrounding gate transistor structure. By using common pillars, insulating films, and gate formation steps for both transistor types, the design reduces manufacturing complexity while maintaining the ability to optimize each transistor type through selective doping and gate electrode configuration.
Solution Approach 2:
The surrounding gate transistor structure serves as a universal platform for both nMOS and pMOS transistors. The same basic structure of pillars, insulating films, and surrounding gates can be used for both transistor types, with differences achieved through selective doping of the pillars and configuration of the gate electrodes. This multi-functionality simplifies the manufacturing process while maintaining optimization capabilities.
Data Source
AI summary
A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second pillar-shaped silicon layers reside on the first and second fin-shaped silicon layers, respectively. An n-type diffusion layer resides in an upper portion of the first fin-shaped silicon layer and in upper and lower portions of the first pillar-shaped silicon layer. A p-type diffusion layer resides in an upper portion of the second fin-shaped silicon layer and upper and lower portions of the second pillar-shaped silicon layer. First and second gate insulating films and metal gate electrodes are around the first and second pillar-shaped silicon layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped silicon layers.