Surrounding Gate Transistor Pillar Impurity Segmentation
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Solution Overview
Problem
There is a demand for pillar-shaped semiconductor devices with higher density, lower power consumption, and higher speed, which existing technologies have not adequately addressed due to limitations in reducing the resistance of N+ layers in surrounding gate transistors.
Innovation Solution
The semiconductor device features a semiconductor pillar with a gate insulating layer and a gate conductor layer, along with impurity regions formed using selective epitaxial crystal growth to reduce resistance and increase integration, while maintaining high crystallinity and stress generation for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MOS transistors are used, then the structure is simple and easy to manufacture, but the integration density is low and chip size is large
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional pillar-shaped surrounding gate transistor structures. The channel extends vertically perpendicular to the substrate surface, with the gate wrapping around the pillar, enabling higher integration density while maintaining manufacturability through established semiconductor processing techniques adapted for vertical structures.
Solution Approach 2:
The gate structure is nested around the semiconductor pillar in a surrounding gate configuration, with the gate insulating layer and gate conductor layer forming concentric layers around the vertical channel. This nested arrangement maximizes the gate's control over the channel while minimizing the device footprint, achieving high integration density.
2Power
If the resistance of N+ layers is reduced to improve speed and lower power consumption, then the device performance improves, but the manufacturing complexity increases
Solution Approach 1:
The impurity regions are segmented into multiple distinct zones: first impurity regions at the lower portions of the pillars, second impurity regions at the upper portions, and third impurity regions within the pillars. This segmentation allows independent optimization of each region's resistance and doping characteristics, enabling reduced overall resistance while maintaining manageable manufacturing complexity through systematic processing steps.
Solution Approach 2:
Different impurity regions are assigned different doping types and concentrations tailored to their specific functional requirements. The first impurity regions use one conductivity type, the second impurity regions use another conductivity type, and the third impurity regions are positioned to optimize carrier concentration locally. This local quality optimization reduces resistance in critical areas without requiring uniform complex structures throughout the entire device.
3Area of stationary object
If higher integration density is achieved through surrounding gate transistors, then the chip size is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The semiconductor pillars are formed first as vertical structures before the gate insulating layer and gate conductor layer are deposited around them. This preliminary formation of the pillar structure provides a well-defined template that guides subsequent processing steps, ensuring precise alignment and positioning of the surrounding gate components, thereby reducing the overall manufacturing precision requirements.
Solution Approach 2:
The vertical pillar structure serves as a self-aligning template for the surrounding gate formation. The gate insulating layer and gate conductor layer naturally conform to the pillar's geometry during deposition, with the pillar's own structure defining the positioning of subsequent layers. This self-service approach minimizes the need for complex alignment procedures and reduces manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a higher-density, lower-power, and faster semiconductor device by reducing the resistance of source and drain regions and enhancing hole mobility, enabling higher performance in SGT circuits.
Implementation Method 1
selective epitaxial crystal growth
Data Source
AI summary
A SiO2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO2 layer. P+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.