Nested Contact Holes in SGT Pillar Semiconductor Devices
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Solution Overview
Problem
There is a demand for higher density and performance in surrounding gate transistors (SGTs) within semiconductor devices, particularly in pillar-shaped configurations, where the integration and connection of wiring conductor layers, contact holes, and metal layers are critical for achieving increased integration.
Innovation Solution
The development of an SGT-including pillar-shaped semiconductor device with a specific structure that includes a semiconductor pillar with a gate insulating layer and a gate conductor layer, interconnected by wiring conductor layers, interlayer insulating layers, and tubular insulating films, along with lead-out conductor layers to enhance connectivity and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring conductor layers, contact holes, and wiring metal layers are formed to connect stacked SGTs, then connectivity between transistor layers is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements nested contact holes where a first contact hole and a second contact hole are positioned such that they overlap or are offset in the vertical direction, with the second contact hole surrounding or being surrounded by the first contact hole. This nested configuration allows multiple wiring layers to be connected through vertically stacked SGTs while maintaining compact spatial arrangement, thereby achieving reliable connectivity without proportionally increasing device complexity.
2Productivity
If multiple SGTs are stacked in a single semiconductor pillar, then integration density increases, but wiring connection complexity increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple SGTs within a single semiconductor pillar to achieve high integration density. By transitioning from planar to three-dimensional architecture, multiple transistors are integrated along the vertical dimension while sharing common substrate area. The nested contact hole structure further manages the wiring complexity by providing organized vertical interconnection paths through the stacked layers.
3Reliability
If contact holes are formed to connect wiring layers at different heights, then interlayer connectivity is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs nested contact holes where the first and second contact holes are positioned to overlap or offset in the vertical direction. This nested arrangement provides inherent alignment guidance during manufacturing, as the overlapping geometry creates natural registration features that reduce the precision requirements for forming subsequent contact holes, thereby maintaining reliable interlayer connectivity while lowering manufacturing barriers.
Data Source
AI summary
A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.