Surrounding Gate Transistor Segmented Gate Parasitic Capacitance
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Solution Overview
Problem
Conventional surrounding gate transistors (SGTs) face challenges in reducing parasitic capacitance, which limits their operating speed and increases power consumption due to the increased area ratio of the gate electrode and the resistance in source and drain regions, especially as the SGT structure is miniaturized.
Innovation Solution
A semiconductor device design that includes a second-conductive type impurity region, a first silicon pillar, a first insulating body surrounding the pillar, and a gate separated by a second insulating body from both the semiconductor substrate and the second silicon pillar, with specific geometrical relationships between the gate and insulating bodies to minimize parasitic capacitance relative to gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the SGT structure is miniaturized to reduce transistor occupancy area, then the area ratio of gate electrode to total transistor occupancy area becomes larger, but the resistance in source and drain regions is increased and ON current is reduced
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate and second gate) positioned at opposite sides of the silicon pillar. This segmentation allows each gate to control a portion of the channel independently, improving carrier injection efficiency and ON current without requiring a larger gate area ratio.
Solution Approach 2:
The transistor structure transitions from a planar configuration to a three-dimensional vertical structure with the gate electrode wrapping around the silicon pillar. This dimensional change enables better control of the channel while maintaining a compact footprint, and the dual-gate configuration adds another layer of control dimension.
2Reliability
If the scale of silicon pillar is reduced to suppress short-channel effects, then area ratio of gate electrode to total transistor occupancy area becomes larger, but resistance in source and drain regions is increased
Solution Approach 1:
The single gate is segmented into two gates positioned at opposite sides of the silicon pillar. This segmentation creates two gate-to-channel interfaces, improving the control over the channel and enabling better suppression of short-channel effects while maintaining lower source and drain resistance through optimized carrier injection paths.
Solution Approach 2:
The first and second insulating films act as intermediaries between the gate electrode and the silicon pillar/source/drain regions. These insulating films with different dielectric constants allow optimization of the electric field distribution, improving short-channel effect suppression while managing the resistance characteristics.
3Reliability
If conventional BG-SGT structure is used to achieve small-diameter channel region and large-diameter source and drain regions, then short-channel effects are suppressed and OFF-current is reduced, but parasitic capacitance between gate and source/drain is not sufficiently low
Solution Approach 1:
The gate electrode is segmented into two separate gates, which reduces the parasitic capacitance between a single large gate and the source/drain regions. By distributing the gate control function across two smaller gates, the total parasitic capacitance is reduced while maintaining effective channel control for low OFF-current.
Solution Approach 2:
The gate electrode is positioned in three dimensions around the silicon pillar rather than being planar. This spatial arrangement, combined with the insulating films, reduces the overlapping area between the gate and source/drain regions, thereby reducing parasitic capacitance while maintaining effective electrostatic control.
4Reliability
If gate electrode area is increased to improve control, then gate capacitance increases, but parasitic capacitance reduction is limited
Solution Approach 1:
The gate electrode is divided into two separate gates, which improves channel control through dual-gate modulation while reducing parasitic capacitance. The segmented configuration allows each gate to effectively control the channel with smaller individual area, and the combined control provides superior electrostatic management compared to a single large gate.
Solution Approach 2:
The first and second insulating films serve as mediators between the gate electrode and the silicon pillar. By selecting insulating materials with appropriate dielectric constants and optimizing their thickness, the electric field distribution is optimized to enhance gate control while minimizing parasitic capacitance coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic capacitance, enhancing the operating speed and reducing power consumption of SGTs by optimizing the distance and cross-sectional area of the gate relative to the insulating bodies, thereby improving the performance of ultra-large-scale integration circuits.
Implementation Method 1
the gate is disposed to be separated from the silicon pillar through a gate oxide layer and to be separated from the source region and the drain region through an interlayer insulating film
Implementation Method 2
a need for ensuring a low parasitic capacitance to achieve an increase in speed and power consumption reduction in an LSI circuit
Data Source
AI summary
It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region (510) formed in a part of a first-conductive type semiconductor substrate (100), a first silicon pillar (810) of an arbitrary cross-sectional shape formed on the second-conductive type impurity region, a first insulating body (310) surrounding a part of a surface of the first silicon pillar, a gate (210) surrounding the first insulating body, and a second silicon pillar (820) which is formed on the first silicon pillar and which includes a second-conductive type impurity region (540). The gate is disposed to be separated from the semiconductor substrate by a second insulating body and is disposed to be separated from the second silicon pillar by the second insulating body. The capacitance between the gate and the semiconductor substrate is less than a gate capacitance, and the capacitance between the gate and the second silicon pillar is less than the gate capacitance.