Surrounding Gate Transistor Fabrication via Self-Aligned Metal Gate
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Solution Overview
Problem
The increasing integration and miniaturization of semiconductor devices, particularly MOS transistors, face challenges in suppressing leak currents and reducing area occupancy due to the difficulty in maintaining necessary current retention, which is exacerbated by the need for precise impurity distribution in nano-scale silicon pillars.
Innovation Solution
A method for producing a Surrounding Gate Transistor (SGT) using a gate last process and self-aligned process, forming a fin-shaped and pillar-shaped semiconductor layer with a metal gate electrode, where the upper portion of the pillar-shaped semiconductor layer functions as an n-type or p-type semiconductor layer by the difference in work function between metal and semiconductor, reducing the number of masks required and eliminating misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three masks are used to form silicon pillar, planar silicon layer, and gate line separately, then each component can be formed with precise control, but the manufacturing process becomes complex and misalignment issues arise
Solution Approach 1:
The patent combines the formation of the gate line and the silicon pillar into a single mask process. The gate line pattern is formed simultaneously with the silicon pillar pattern using one mask, eliminating the need for separate masking steps. This merging of operations reduces process complexity and prevents misalignment between the gate line and silicon pillar while maintaining precise component formation.
2Manufacturing precision
If ion implantation is used to form diffusion layer in upper portion of silicon pillar, then impurity distribution can be controlled, but the process becomes difficult due to polysilicon gate coverage and nano-scale dimensions
Solution Approach 1:
The patent performs ion implantation to form the diffusion layer in the upper portion of the silicon pillar before forming the polysilicon gate. By executing the impurity introduction step in advance, while the pillar structure is accessible and larger in dimension, the process avoids the difficulties of subsequent ion implantation through narrow gaps. This preliminary action ensures precise impurity distribution is achieved before the gate structure complicates further processing.
3Adaptability or versatility
If metal gate-last process is employed, then both metal gate process and high-temperature process can be achieved, but diffusion layer formation becomes more difficult due to polysilicon gate coverage
Solution Approach 1:
The patent executes the ion implantation step to form the diffusion layer before the polysilicon gate is deposited in the metal gate-last process sequence. This timing arrangement maintains the versatility of combining metal gate with high-temperature processing while avoiding the manufacturing difficulty of forming diffusion layers after gate coverage. The preliminary formation of the diffusion layer ensures impurity distribution is established before the gate structure is in place.
4Ease of operation
If channel concentration is set to low impurity concentration of 10^17 cm^-3 or less, then threshold voltage can be controlled by gate material work function, but impurity presence in silicon pillar becomes difficult to achieve
Solution Approach 1:
The patent performs ion implantation to introduce impurities into the silicon pillar at a stage when the structure is accessible and before final gate formation. This preliminary impurity introduction establishes the necessary doping profile with precise concentration control (10^17 cm^-3 or less) in the channel region, enabling subsequent threshold voltage control through gate material work function selection without compromising impurity distribution precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient formation of SGTs with reduced steps, eliminating the need for a diffusion layer in the upper portion of the pillar-shaped semiconductor layer and ensuring accurate contact formation, thereby enhancing current retention and reducing area occupancy while maintaining precise impurity distribution.
Implementation Method 1
forming a metal-semiconductor compound
Implementation Method 2
the upper portion of the pillar-shaped semiconductor layer is made to function as an n-type semiconductor layer or a p-type semiconductor layer by the difference in work function between metal and semiconductor
Data Source
AI summary
A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate electrode is around the first gate insulating film and a metal gate line is connected to the gate electrode. A second gate insulating film is around a sidewall of an upper portion of the pillar-shaped semiconductor layer and a first contact made of a second metal surrounds the second gate insulating film. An upper portion of the first contact is electrically connected to an upper portion of the pillar-shaped semiconductor layer, and a third contact resides on the metal gate line. A lower portion of the third contact is made of the second metal.