Semiconductor Device Sidewall Structure for SGT Integration
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Solution Overview
Problem
In semiconductor integrated circuits, finer MOS transistors face challenges in suppressing leak currents and reducing circuit area, leading to issues like short-circuiting and difficulty in achieving high integration due to the limitations of conventional surrounding gate transistor (SGT) manufacturing methods, particularly with the use of nitride films and epitaxial growth.
Innovation Solution
A semiconductor device with a SGT structure featuring a pillar-shaped silicon layer, a laminated sidewall structure of insulating film and polysilicon, where the polysilicon is electrically connected to the diffusion layer, reducing resistance and allowing for higher integration by controlling the etching process and impurity distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nitride film sidewall is formed on the silicon pillar to prevent short-circuiting, then short-circuiting between contact and gate is prevented, but the etching selection ratio decreases and contact etching cannot be stopped accurately
Solution Approach 1:
The sidewall structure is segmented into two distinct materials: a lower nitride film portion and an upper oxide film portion. The nitride film provides etching resistance to prevent short-circuiting, while the oxide film portion provides high etching selection ratio to enable precise contact etching stopping. This segmentation allows each material to fulfill its specific function without compromising the other.
Solution Approach 2:
The sidewall is constructed as a composite structure combining nitride film and oxide film in a laminated configuration. The nitride film layer (first film) is formed first to provide baseline etching resistance, followed by the oxide film layer (second film) that provides superior etching selectivity. This composite approach leverages the complementary properties of both materials to simultaneously achieve short-circuit prevention and precise etching control.
2Productivity
If the silicon pillar diameter is reduced to achieve higher integration, then circuit area is decreased, but the flat area decreases and etching selection ratio is further reduced
Solution Approach 1:
By using a composite sidewall structure with both nitride film and oxide film, the patent maintains high etching selection ratio even when the silicon pillar diameter is reduced. The oxide film portion specifically addresses the etching selection ratio issue that arises with smaller pillar sizes, enabling continued miniaturization without sacrificing manufacturing precision.
Solution Approach 2:
The sidewall structure applies different material properties at different locations: the nitride film is positioned at the lower portion where mechanical strength and baseline etching resistance are needed, while the oxide film is positioned at the upper portion where high etching selection ratio is critical for contact formation. This local differentiation of material properties optimizes performance for each specific functional requirement.
3Ease of manufacture
If deep diffusion layer is formed to allow ion implantation into thin silicon pillar, then ion implantation is achieved, but the diffusion layer widens in lateral direction making higher integration difficult
Solution Approach 1:
The thin oxide film sidewall acts as a confining structure that guides and restricts the lateral spread of the diffusion layer during ion implantation. By forming the diffusion layer through the thin oxide film, the patent achieves effective ion implantation into the thin silicon pillar while the oxide film boundaries prevent excessive lateral widening, thus maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases the resistance in the upper portion of the silicon pillar, prevents short-circuiting, and enables higher integration by stopping contact etching accurately and forming shallow junctions, thus improving the performance of transistors.
Implementation Method 1
the polysilicon of the sidewall decreases a resistance in an upper portion of the silicon pillar
Implementation Method 2
the diffusion layer is formed in an upper portion of the silicon pillar by ion implantation
Data Source
AI summary
A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer.