Surrounding Gate Transistor Silicide Self-Alignment
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Solution Overview
Problem
The challenge is to reduce the occupancy area of Surrounding Gate Transistors (SGTs) in high-integration and high-performance logic devices, such as CPUs, without increasing the parasitic resistance in the source/drain region, while maintaining minimal distance between SGTs and contacts, especially in SRAM circuits.
Innovation Solution
The solution involves forming a silicide layer in a self-alignment manner on the upper and lower diffusion layers of the pillar-shaped semiconductor layer, using a first dielectric film to protect the sidewall during silicide formation, and then removing it to cover the source/drain and gate electrode regions with a second dielectric film as a contact stopper, followed by a third dielectric film as an interlayer, optimizing the thickness ratios of these films to minimize the SGT occupancy area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional SGT structure with multiple dielectric films is used, then the source/drain region is well-protected during fabrication, but the occupancy area of the SGT increases
Solution Approach 1:
The patent removes the first dielectric film (sidewall protection film) after silicide formation, extracting only the necessary protective function during fabrication while eliminating unnecessary material that increases occupancy area. This allows the source/drain region to be adequately protected during silicide formation but reduces the final structure size.
Solution Approach 2:
The patent transitions from a planar transistor structure to a vertical SGT structure where drain, gate, and source are arranged in the vertical direction. This dimensional change significantly reduces the occupancy area while maintaining transistor functionality and allowing self-aligned silicide formation.
2Area of stationary object
If the distance between SGT and contact is reduced to increase integration density, then circuit area decreases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent forms the silicide layer in a self-aligned manner before forming the contact, using the source/drain region itself as the alignment reference. This preliminary action establishes precise positioning that maintains manufacturing precision even when the final distance between SGT and contact is reduced for higher integration density.
3Reliability
If self-aligned silicide formation is implemented to reduce parasitic resistance, then transistor performance improves, but process complexity increases
Solution Approach 1:
The patent uses the source/drain region and gate structure themselves as alignment references for silicide formation, allowing the structure to define its own fabrication boundaries. This self-service approach achieves self-aligned silicide formation that reduces parasitic resistance while avoiding the need for additional complex alignment processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the occupancy area of SGTs and the distance between SGTs and contacts, leading to a decrease in the overall logic circuit area, particularly in SRAM cells, by limiting the dielectric film coverage to a contact-stopper silicon nitride film, thereby enhancing transistor performance and integration density.
Implementation Method 1
a silicide layer formed in upper surfaces of upper and lower diffusion layers in a self-alignment manner
Implementation Method 2
the silicide layer is formed after forming a first dielectric film on a sidewall of the pillar-shaped semiconductor layer to protect the sidewall of the pillar-shaped semiconductor layer during formation of the silicide layer
Implementation Method 3
a second dielectric film formed, after forming the silicide layer and then removing the first dielectric film, in such a manner as to cover a source/drain region formed in the underneath portion of the pillar-shaped semiconductor layer, the gate electrode formed on the sidewall of the pillar-shaped semiconductor layer, and a source/drain region formed on the upper portion of the pillar-shaped semiconductor layer
Implementation Method 4
a third dielectric film covering the second dielectric film to serve as an interlayer film
Data Source
AI summary
It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a substrate, and the gate is formed to surround a pillar-shaped semiconductor layer. The semiconductor device comprises: a silicide layer formed in an upper surface of each of upper and lower diffusion layers formed in upper and underneath portions of the pillar-shaped semiconductor layer, in a self-alignment manner, wherein the silicide layer is formed after forming a first dielectric film on a sidewall of the pillar-shaped semiconductor layer to protect the sidewall of the pillar-shaped semiconductor layer during formation of the silicide layer; and a second dielectric film formed, after forming the silicide layer and then removing the first dielectric film, in such a manner as to cover a source/drain region formed in the underneath portion of the pillar-shaped semiconductor layer, the gate electrode formed on the sidewall of the pillar-shaped semiconductor layer, and a source/drain region formed on the upper portion of the pillar-shaped semiconductor layer.