Surround Gate SRAM Cell Area Reduction via Shared Diffusion
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Solution Overview
Problem
Current SRAM cell designs using Surrounding Gate Transistors (SGTs) face challenges in reducing the SRAM cell area due to the presence of unnecessary contacts and high resistance word lines, which increase the cell area and hinder performance in LSI circuits.
Innovation Solution
The design incorporates four MOS transistors and two load resistor elements arranged on a dielectric film, with shared diffusion layers and contact plugs made of semiconductor or metal materials, optimizing the layout to minimize cell area and reduce resistance by eliminating unnecessary contacts and using high-efficiency load resistor elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional SGT-SRAM cell structure with separate contacts for storage nodes is used, then data access is enabled, but SRAM cell area increases due to unnecessary contacts
Solution Approach 1:
The patent merges the storage node diffusion layer with the source/drain diffusion layer of the access transistor. The storage node is formed by the same diffusion process that creates the source/drain regions, eliminating the need for separate contact structures to access storage nodes. This integration reduces the number of contacts required and decreases the overall cell area.
Solution Approach 2:
The patent extracts and eliminates unnecessary contacts from the conventional SGT-SRAM structure. By reconfiguring the diffusion layers to serve dual purposes (both as transistor source/drain and as storage nodes), the design removes redundant contact elements that would otherwise be required to access the storage nodes separately.
2Reliability
If polysilicon word line is used, then gate control is achieved, but word line resistance increases reducing performance
Solution Approach 1:
The patent changes the material parameter of the word line from polysilicon to a lower-resistance material such as metal. This parameter change directly reduces the parasitic resistance of the word line, improving signal integrity and overall device performance while maintaining the gate control function.
3Object-generated harmful factors
If load resistor elements are formed by polysilicon interconnection layer, then resistive load is provided, but SRAM cell area significantly increases
Solution Approach 1:
The patent merges the load resistor function with existing diffusion layers and interconnection structures. Instead of adding separate polysilicon interconnection layers dedicated to forming load resistors, the design utilizes the inherent resistive properties of shared diffusion regions and integrated interconnection paths, thereby providing the necessary resistive load without increasing cell area.
Data Source
AI summary
It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.