SHA-256 Quantum Circuit Path Balancing for Shorter Critical Paths
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Solution Overview
Problem
Existing SHA-256 quantum circuits have a long critical path length, which determines their execution time, making them inefficient for quantum computing applications.
Innovation Solution
The design of an SHA-256 quantum circuit that reduces the critical path length by applying a path balancing technique, specifically by creating the d+T1 value first instead of T1, and iteratively applying this technique to reduce the number of adders and subtractors in the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the conventional SHA-256 quantum circuit design is used, then the circuit can perform standard SHA-256 computations, but the critical path length is long (6 adders) resulting in slow execution time
Solution Approach 1:
The patent segments the addition operations into two distinct types: carry-propagate additions (CP-adders) and ripple-carry additions (RC-adders). This segmentation allows different parts of the circuit to use different addition methods with optimized critical path lengths, reducing the overall execution time while maintaining computational correctness
Solution Approach 2:
The patent dynamically selects between different addition methods (CP-adder or RC-adder) based on the specific computational requirements of each round. The circuit configuration adapts the addition strategy based on the round number and data flow requirements, optimizing the critical path length for each specific computation step
2Productivity
If more adders are used to reduce the critical path length, then the execution time decreases, but the circuit complexity and number of gates increases
Solution Approach 1:
The patent changes the parameter of addition method from a fixed approach to a variable approach, selecting between carry-propagate and ripple-carry additions based on computational needs. This parameter change allows optimization of the critical path length without uniformly increasing the number of adders throughout the entire circuit
Solution Approach 2:
The patent applies path balancing techniques selectively to specific critical paths within the circuit rather than uniformly across all paths. This partial application of optimization reduces the critical path length where needed while avoiding unnecessary complexity in non-critical sections
Data Source
AI summary
Disclosed herein SHA-256 quantum circuit design apparatus and method. According to an embodiment of the present disclosure, there is provided an SHA-256 quantum circuit design apparatus comprising: a reception unit configured to receive an SHA-256 quantum circuit having a length of a critical path consisting of six adders; and a design unit configured to design a first SHA-256 quantum circuit having the critical path length reduced to a first value by applying a path balancing technique to the received SHA-256 quantum circuit and to design a second SHA-256 quantum circuit having the critical path length reduced to a second value by applying the path balancing technique to the first SHA-256 quantum circuit to output a d+T1 value first.